Daniel E. Holcomb

PROFILE

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Aliases
Dan Holcomb, Daniel Edward Holcomb, Daniel Holcomb
Publication record
76 papers · 3,038 citations · H-index 27

PAPERS

Fault Recovery from Multi-Tenant FPGA Voltage Attacks
20231 citationsauthor #3
A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAs
20239 citationsauthor #3
Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud
202210 citationsauthor #5
Accelerating BGP Configuration Verification Through Reducing Cycles in SMT Constraints
20223 citationsauthor #3
Voltage Sensor Implementations for Remote Power Attacks on FPGAs
202226 citationsauthor #7
Know Time to Die - Integrity Checking for Zero Trust Chiplet-based Systems Using Between-Die Delay PUFs
20226 citationsauthor #2
Precise Fault Injection to Enable DFIA for Attacking AES in Remote FPGAs
20228 citationsauthor #3
Mitigating Voltage Attacks in Multi-Tenant FPGAs
202128 citationsauthor #2
Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs
202158 citationsauthor #3
Characterization of IOBUF-based Ring Oscillators
20213 citationsauthor #2
Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs
202140 citationsauthor #4
Power Distribution Attacks in Multitenant FPGAs
202029 citationsauthor #2
Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs
202048 citationsauthor #4
Techniques to Reduce Switching and Leakage Energy in Unrolled Block Ciphers
20204 citationsauthor #2
Power Wasting Circuits for Cloud FPGA Attacks
202040 citationsauthor #2
Efficient Register Renaming Architectures for 8-bit AES Datapath at 0.55 pJ/bit in 16-nm FinFET
20208 citationsauthor #3
COUNTERFOIL: Verifying Provenance of Integrated Circuits using Intrinsic Package Fingerprints and Inexpensive Cameras
202015 citationsauthor #3
Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud
202012 citationsauthor #5
Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs
202025 citationsauthor #7
ASHES 2019: 3rd Workshop on Attacks and Solutions in Hardware Security
20190 citationsauthor #2
Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques
201982 citationsauthor #3
Characterizing Power Distribution Attacks in Multi-User FPGA Environments
201962 citationsauthor #2
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration
201946 citationsauthor #6
Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility
20199 citationsauthor #2
Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays
20191 citationsauthor #3
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs
201938 citationsauthor #6
Temperature-Based Hardware Trojan For Ring-Oscillator-Based TRNGs
20195 citationsauthor #2
Bimodal Oscillation as a Mechanism for Autonomous Majority Voting in PUFs
20185 citationsauthor #5
Algorithmic Obfuscation over GF(2m)
20180 citationsauthor #2
FPGA Side Channel Attacks without Physical Access
2018121 citationsauthor #6
Survey on Applications of Formal Methods in Reverse Engineering and Intellectual Property Protection
201812 citationsauthor #5
A provable key destruction scheme based on memristive crossbar arrays
201879 citationsauthor #8
SAT-based reverse engineering of gate-level schematics using fault injection and probing
20189 citationsauthor #5
ASHES 2018- Workshop on Attacks and Solutions in Hardware Security
20182 citationsauthor #3
Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits
201755 citationsauthor #5
Improving reliability of weak PUFs via circuit techniques to enhance mismatch
201712 citationsauthor #3
Privacy leakages in approximate adders
20179 citationsauthor #2
An improved clocking methodology for energy efficient low area AES architectures using register renaming
20177 citationsauthor #2
Design automation for obfuscated circuits with multiple viable functions
20179 citationsauthor #3
Nanoscale CMOS Memory-Based Security Primitive Design
20170 citationsauthor #1
Threshold-based obfuscated keys with quantifiable security against invasive readout
20176 citationsauthor #2
Energy Efficient Loop Unrolling for Low-Cost FPGAs
201711 citationsauthor #3
A clockless sequential PUF with autonomous majority voting
201614 citationsauthor #2
A Design Methodology for Stealthy Parametric Trojans and Its Application to Bug Attacks
201638 citationsauthor #3
Oracle-guided incremental SAT solving to reverse engineer camouflaged logic circuits
201648 citationsauthor #4
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement
201612 citationsauthor #4
Persistent Clocks for Batteryless Sensing Devices
201682 citationsauthor #5
Reverse engineering of irreducible polynomials in GF(2m) arithmetic
20163 citationsauthor #2
Energy Optimization of Unrolled Block Ciphers Using Combinational Checkpointing
20168 citationsauthor #2
Reliable PUF design using failure patterns from time-controlled power gating
20168 citationsauthor #2
Using Statistical Models to Improve the Reliability of Delay-Based PUFs
201635 citationsauthor #3
LLPA: Logic State Based Leakage Power Analysis
20162 citationsauthor #3
Security Evaluation and Enhancement of Bistable Ring PUFs
201546 citationsauthor #3
Reliable Physical Unclonable Functions Using Data Retention Voltage of SRAM Cells
201545 citationsauthor #3
Probable cause: The deanonymizing effects of approximate DRAM
201535 citationsauthor #3
PUFs at a glance
2014207 citationsauthor #2
An Evaluation of {ECG} use in Cryptography for Implantable Medical Devices and Body Area Networks
20140 citationsauthor #3
Refreshing Thoughts on DRAM : Power Saving vs . Data Integrity
201416 citationsauthor #3
Compositional Performance Verification of Network-on-Chip Designs
20145 citationsauthor #1
QBF-Based Synthesis of Optimal Word-Splitting in Approximate Multi-Level Storage Cells
20143 citationsauthor #1
Formal Verification and Synthesis for Quality-of-Service in On-Chip Networks
20135 citationsauthor #1
Compositional performance verification of NoC designs
201210 citationsauthor #1
DRV-Fingerprinting: Using Data Retention Voltage of SRAM Cells for Chip Identification
201237 citationsauthor #1
TARDIS: Time and Remanence Decay in SRAM to Implement Secure Protocols on Embedded Devices without Clocks
201291 citationsauthor #3
Abstraction-Based Performance Analysis of NoCs
20116 citationsauthor #1
Abstraction-based performance verification of NoCs
20117 citationsauthor #1
Counterexample-guided SMT-driven optimal buffer sizing
20115 citationsauthor #2
Low-power sub-threshold design of secure physical unclonable functions
201084 citationsauthor #2
Design as you see FIT: System-level soft error analysis of sequential circuits
200952 citationsauthor #1
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
2009807 citationsauthor #1
Algorithms for Green Buildings: Learning-Based Techniques for Energy Prediction and Fault Diagnosis
200922 citationsauthor #1
Robustness Enhancement Techniques for Minimum-Sized Subthreshold Circuits in Advanced Technologies
20080 citationsauthor #1
Robustness Optimization in Subthreshold Circuits
20080 citationsauthor #1
Device Sizing Techniques for High Yield Minimum-Energy Subthreshold Circuits
20080 citationsauthor #1
Initial SRAM State as a Fingerprint and Source of True Random Numbers for RFID Tags
2007356 citationsauthor #1
Randomness in Integrated Circuits with Applications in Device Identification and Random Number Generation
20071 citationsauthor #1

TIMELINE

2007 357 citations

2008 0 citations

2009 881 citations

2010 84 citations

2011 18 citations

2012 138 citations

2013 5 citations

2014 231 citations

2015 126 citations

2016 250 citations

2017 109 citations

2018 228 citations

2019 243 citations

2020 181 citations

2021 129 citations

2022 53 citations

2023 10 citations

Daniel E. Holcomb

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