On-Chip Sparse Learning Acceleration With CMOS and Resistive Synaptic Devices

No abstract is available for this paper.

• Publication year

  2015

• Venue

  IEEE transactions on nanotechnology

• Publication date

  2015-09-15

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/TNANO.2015.2478861
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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  2011influential reference
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  2010cited by this paper
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  2005influential reference
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  2005cited by this paper
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  1999cited by this paper
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  1998influential reference
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  1996cited by this paper
• © Institute of Mathematical Statistics, 2004 LEAST ANGLE REGRESSION

  year unknowninfluential reference

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