Optimizing off-chip accesses in multicores

No abstract is available for this paper.

• Publication year

  2015

• Venue

  ACM-SIGPLAN Symposium on Programming Language Design and Implementation

• Publication date

  2015-06-03

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1145/2737924.2737989
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Optimizing Off-Chip Accesses in Manycores

  2015cited by this paper
• Traffic management: a holistic approach to memory placement on NUMA systems

  2013cited by this paper
• Application-to-core mapping policies to reduce memory system interference in multi-core systems

  2013cited by this paper
• Replacement techniques for dynamic NUCA cache designs on CMPs

  2013cited by this paper
• Matching memory access patterns and data placement for NUMA systems

  2012cited by this paper
• Unified memory optimizing architecture: memory subsystem control with a unified predictor

  2012cited by this paper
• Optimal memory controller placement for chip multiprocessor

  2011cited by this paper
• Neighborhood-aware data locality optimization for NoC-based multicores

  2011cited by this paper
• Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior

  2010cited by this paper
• ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers

  2010cited by this paper
• Feedback-directed page placement for ccNUMA via hardware-generated memory traces

  2010cited by this paper
• PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches

  2009cited by this paper
• Achieving predictable performance through better memory controller placement in many-core CMPs

  2009cited by this paper
• Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors

  2009cited by this paper
• Distance-aware round-robin mapping for large NUCA caches

  2009cited by this paper
• A flexible data to L2 cache mapping approach for future multicore processors

  2006cited by this paper
• Networks on Chips: Technology and Tools

  2006influential reference
• Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

  2006cited by this paper
• Managing Wire Delay in Large Chip-Multiprocessor Caches

  2004cited by this paper
• Compiler Techniques for the Distribution of Data and Computation

  2003cited by this paper
• SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance

  2001cited by this paper
• Symbiotic jobscheduling for a simultaneous mutlithreading processor

  2000cited by this paper
• Data transformations for eliminating conflict misses

  1998influential reference
• Splitting Data Objects to Increase Cache Utilization ( Preliminary Version , 9 th October 1998 )

  1998cited by this paper
• Non-singular data transformations: definition, validity and applications

  1997cited by this paper
• Compiler-directed page coloring for multiprocessors

  1996cited by this paper
• Operating system support for improving data locality on CC-NUMA compute servers

  1996cited by this paper
• Optimizing Data Locality by Array Restructuring

  1995cited by this paper
• Data and computation transformations for multiprocessors

  1995cited by this paper
• Theory of linear and integer programming

  1986cited by this paper

• Architecture-Aware Currying

  2023cites this paper
• Fine-Granular Computation and Data Layout Reorganization for Improving Locality

  2022cites this paper
• Distance-in-time versus distance-in-space

  2021cites this paper
• Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures

  2021cites this paper
• Compiler support for near data computing

  2021cites this paper
• Enhancing Address Translations in Throughput Processors via Compression

  2020cites this paper
• Quantifying Data Locality in Dynamic Parallelism in GPUs

  2019cites this paper
• Co-optimizing memory-level parallelism and cache-level parallelism

  2019cites this paper
• Computing with Near Data

  2019cites this paper
• Architecture-Aware Approximate Computing

  2019cites this paper
• Architecture-Aware Approximate Computing

  2019cites this paper
• A Survey of Compiler Optimization Techniques

  2019cites this paper
• Enhancing computation-to-core assignment with physical location information

  2018influential citation
• Quantifying and Optimizing Data Access Parallelism on Manycores

  2018cites this paper
• Computing with Near Data

  2018cites this paper
• Quantifying Data Locality in Dynamic Parallelism in GPUs

  2018cites this paper
• Controlled Kernel Launch for Dynamic Parallelism in GPUs

  2017cites this paper
• POSTER: Location-Aware Computation Mapping for Manycore Processors

  2017cites this paper
• DEMM: A Dynamic Energy-Saving Mechanism for Multicore Memories

  2017cites this paper
• Data Movement Aware Computation Partitioning

  2017cites this paper
• Quantifying the Potential Benefits of On-chip Near-Data Computing in Manycore Processors

  2017cites this paper
• Silicon photonic memory interconnect for many-core architectures

  2016cites this paper