Crosstalk avoidance codes for 3D VLSI

No abstract is available for this paper.

• Publication year

  2013

• Venue

  Design, Automation and Test in Europe

• Publication date

  2013-03-18

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.7873/DATE.2013.338
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling

  2011cited by this paper
• Low-Power and Reliable Clock Network Design for Through-Silicon Via (TSV) Based 3D ICs

  2011cited by this paper
• ILP-based inter-die routing for 3D ICs

  2011cited by this paper
• Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC

  2011influential reference
• Stress-driven 3D-IC placement with TSV keep-out zone and regularity study

  2010cited by this paper
• Pre-bond testable low-power clock tree design for 3D stacked ICs

  2009cited by this paper
• Enabling 3D-IC foundry technologies for 28 nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking

  2009cited by this paper
• Efficient On-Chip Crosstalk Avoidance CODEC Design

  2009cited by this paper
• Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

  2009cited by this paper
• A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid Cu-adhesive bonding

  2008cited by this paper
• Forbidden transition free crosstalk avoidance CODEC design

  2008cited by this paper
• 3D stacked IC demonstration using a through Silicon Via First approach

  2008cited by this paper
• Through-silicon via and die stacking technologies for microsystems-integration

  2008cited by this paper
• Temperature-aware routing in 3D ICs

  2006cited by this paper
• Efficient thermal placement of standard cells in 3D ICs using a force directed approach

  2003cited by this paper
• The International Technology Roadmap for Semiconductors—Perspectives and challenges for the next 15 years

  2002cited by this paper

• Weighted Coding Scheme for Noise Reduction in Silicon Interposer of HBM

  2026influential citation
• WITCH: WeIghTed Coding Scheme for Crosstalk Reduction in High Bandwidth Memory

  2025cites this paper
• FNS-CATF-CAC: An Efficient Crosstalk Avoidance Code to Reduce the Switching Activity in TSV Arrays

  2025influential citation
• Dy-MFNS-CAC: An Encoding Mechanism to Suppress the Crosstalk and Repair the Hard Faults in Rectangular TSV Arrays

  2024cites this paper
• Low-Energy Line Codes for On-Chip Networks

  2024cites this paper
• Mosaic-3C1S: A Low Overhead Crosstalk Suppression Scheme for Rectangular TSV Array

  2023cites this paper
• A Global Self-Repair Method for TSV Arrays With Adaptive FNS-CAC Codec

  2022influential citation
• A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems

  2022cites this paper
• 3D IC Packaging Utilizing a Metal Structure for Heat Reduction, Noise Shielding, and High Interconnect Density

  2021cites this paper
• Built-in Self-Test and Fault Localization for Inter-Layer Vias in Monolithic 3D ICs

  2021cites this paper
• Characterization of corner/edge effects of through silicon via arrays and layout optimization in 3D integrated circuits

  2021cites this paper
• TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems

  2020cites this paper
• A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

  2020cites this paper
• A Non-Blocking Non-Degrading Multiple Defects Link Testing Method for 3D-Networks-on-Chip

  2020cites this paper
• 2D Parity Product Code for TSV online fault correction and detection

  2020cites this paper
• Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment

  2019cites this paper
• Crosstalk-aware TSV-buffer Insertion in 3D IC

  2019cites this paper
• An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs

  2019cites this paper
• 2D-PPC: A single-correction multiple-detection method for Through-Silicon-Via Faults

  2019cites this paper
• 3DCAM: A Low Overhead Crosstalk Avoidance Mechanism for TSV-Based 3D ICs

  2019influential citation
• Edge effect aware low-power crosstalk avoidance technique for 3D integration

  2019influential citation
• AM3D: An accurate crosstalk probability modeling to predict channel delay in 3D ICs

  2019cites this paper
• Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration

  2018influential citation
• An Exhaustive Search of the Optimal 6C Level Static Shielding Scheme for Rectangle TSV Arrays

  2018influential citation
• Coding Approach for Low-Power 3D Interconnects

  2018cites this paper
• Edge effects on the TSV array capacitances and their performance influence

  2017influential citation
• Edge effect aware crosstalk avoidance technique for 3D integration

  2017influential citation
• High-Level Energy Estimation for Submicrometric TSV Arrays

  2017cites this paper
• An Enhancement of Crosstalk Avoidance Code Based on Fibonacci Numeral System for Through Silicon Vias

  2017influential citation
• Data Transfer Performance Analysis and Enhancement of Critical 3D Interconnects in a 3D SiP Based on Communication Channel Modeling Methodology

  2017cites this paper
• 3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICs

  2017cites this paper
• Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC

  2017cites this paper
• A crosstalk avoidance method combining crosstalk avoidance code with shielding wire technique

  2016influential citation
• 3D-DPS: An Efficient 3D-CAC for Reliable Data Transfer in 3D ICs

  2016influential citation
• Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs

  2016cites this paper
• Capacitive and Inductive TSV-to-TSV Resilient Approaches for 3D ICs

  2016influential citation
• Capacitive Coupling Mitigation for TSV-based 3D ICs

  2015influential citation
• Coupling Mitigation in 3-D Multiple-Stacked Devices

  2015cites this paper
• Analytical Fault Tolerance Assessment and Metrics for TSV-Based 3D Network-on-Chip

  2015cites this paper
• CHIP/PACKAGE CO-DESIGN METHODOLOGIES FOR RELIABLE 3D ICS

  2015cites this paper
• Novel crosstalk minimization code for 3D IC

  2015cites this paper
• A crosstalk avoidance scheme based on re-layout of signal TSV

  2015cites this paper
• TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip

  2014cites this paper
• 3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition code

  2014influential citation
• Partial coding algorithm for area and energy efficient crosstalk avoidance codes implementation

  2013cites this paper