An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors

No abstract is available for this paper.

• Publication year

  2003

• Venue

  IEEE Trans. Computers

• Publication date

  2003-11-01

• Fields of study

  Computer Science

• Identifiers
  DOI 10.1109/TC.2003.1244948
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Computer Graphics - Principles and Practice, 3rd Edition

  2014cited by this paper
• Ati radeon hyperz technology

  2000cited by this paper
• The Wild World of 3D Graphics Chips

  2000cited by this paper
• Neon: A (Big) (Fast) Single-Chip 3D Workstation Graphics Accelerator

  1999cited by this paper
• Parallel texture caching

  1999cited by this paper
• Implementing Neon: a 256-bit graphics accelerator

  1999cited by this paper
• Neon: a single-chip 3D workstation graphics accelerator

  1998cited by this paper
• Designing a PC Game Engine

  1998cited by this paper
• The Truga001: A Scalable Rendering Processor

  1998cited by this paper
• Unsolved problems and opportunities for high-quality, high-performance 3D graphics on a PC platform

  1998cited by this paper
• Prefetching in a texture cache architecture

  1998cited by this paper
• Computer graphics: Principles and practice

  1997cited by this paper
• The Design And Analysis Of A Cache Architecture For Texture Mapping

  1997cited by this paper
• InfiniteReality: a real-time graphics system

  1997cited by this paper
• The Setup for Triangle Rasterization

  1996cited by this paper
• Wisconsin Architectural Research Tool Set

  1993cited by this paper
• Hierarchical Z-buffer visibility

  1993cited by this paper
• The OpenGL Reference Manual

  1992cited by this paper

• David II: 효과적인 메모리 시스템을 가지는

  2019cites this paper
• Combination of Collision Detection and Visibility Algorithms in Simulation of the Effective Placement of Anti-air Elements

  2017cites this paper
• A pixel pipeline architecture with selective z-test scheme for 3D graphics processors

  2013cites this paper
• Implementation of a 3D Graphics Rasterizer with Texture and Slim Shader on FPGA

  2013cites this paper
• A Memory-Efficient Unified Early Z-Test

  2011cites this paper
• Series-parallel pipeline architecture for high-resolution catadioptric panoramic unwrapping

  2010cites this paper
• The design of compressed memory system for depth data in 3D rendering processors

  2010cites this paper
• 3D graphics cache system to maximize memory utilization for an embedded system

  2009cites this paper
• Area-efficient pixel rasterization and texture coordinate interpolation

  2008cites this paper
• A hybrid real-time visible surface solution for rays with a common origin and arbitrary directions

  2008cites this paper
• Implementation of 3D graphics accelerator using full pipeline scheme on FPGA

  2008cites this paper
• An Area Efficient Early ${Z}$ -Test Method for 3-D Graphics Rendering Hardware

  2008cites this paper
• Clipping-ratio-independent 3D graphics clipping engine by dual-thread algorithm

  2008cites this paper
• A Pixel Pipeline Architecture with Effective Visibility Test for 3D Graphics Accelerators

  2007cites this paper
• Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics Hardware

  2007cites this paper
• A consistency-free memory architecture for sort-last parallel rendering processors

  2007cites this paper
• Simulation and development environment for mobile 3D graphics architectures

  2007cites this paper
• An effective visibility culling method based on cache block

  2006cites this paper
• Design and Implementation of Power-Aware Mobile 3 D Graphics

  2006cites this paper
• An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications

  2006cites this paper
• A Processor Architecture with Effective Memory System for Sort-Last Parallel Rendering

  2006cites this paper
• Design of a Parallel Rendering Processor Architecture with Effective Memory System

  2006cites this paper
• A Low-Power Implementation of 3D Graphics System for Embedded Mobile Systems

  2006cites this paper
• An effective visibility culling method for 3D rendering processor

  2005influential citation
• A pixel cache architecture with selective placement scheme based on z-test result

  2005cites this paper
• Visibility Culling per Cache Block with Tiling-Traversal Algorithm

  2004cites this paper
• 3D graphics accelerator platform for mobile devices

  2004cites this paper