A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model

Simulating human brain with hardware has been an attractive project for many years, since memory is one of the fundamental functions of our brains. Several memory models have been proposed up to now in order to unveil how the memory is organized in the brain. In this paper, we adopt spatio-temporal memory (STM) model, in which both associative memory and episodic memory are analyzed and emulated, as the reference of our hardware network architecture. Furthermore, some reasonable adaptations are carried out for the hardware implementation. We finally implement this memory model on FPGA, and additional experiments are performed to fine tune the parameters of our network deployed on FPGA.

• Publication year

  2019

• Venue

  Frontiers in Neuroscience

• Publication date

  2019-08-09

• Fields of study

  Medicine, Computer Science, Engineering

• Identifiers
  DOI 10.3389/fnins.2019.00835PMID 31447641PMCID 6697024
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar, PubMed

• No claims are published for this paper.

• No concepts are published for this paper.

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