Performance optimised architectures of Piccolo block cipher for low resource IoT applications

Radio frequency identification (RFID) and wireless sensor networks (WSNs) are the devices with constrained environments, have been expanded with the current trend of network capabilities and ubiquitous computing, which spread wings of internet of things (IoT). Piccolo is one of the ultra lightweight block cipher, uses 64-bit plaintext and two versions of keys 80 and 128-bit, makes them suitable for low computing devices. Different hardware architectures have been proposed to make them suitable for the low area, low power, and high speed applications. The strategies like loop rolled, parallel round based and pipelined architectures are employed to optimise the hardware design for low resource applications. The proposed architectures have been implemented on field programmable gate arrays (FPGA) achieving throughput of 691.54, 613.26, and 1195.54 Mbps as well as slice count of 47 results in low area and low power.

• Publication year

  2020

• Venue

  International Journal of High Performance Systems Architecture

• Publication date

  2020-05-01

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1504/ijhpsa.2020.10029194
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• No references are available for this paper.

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