An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

No abstract is available for this paper.

• Publication year

  2007

• Venue

  2007 Design, Automation & Test in Europe Conference & Exhibition

• Publication date

  2007-04-16

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/DATE.2007.364574
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• System level methodology for programming CMP based multi-threaded network processor architectures

  2005cited by this paper
• Profiling and mapping of parallel workloads on network processors

  2005cited by this paper
• Application analysis and resource mapping for heterogeneous network processor architectures

  2005cited by this paper
• Towards a generic programming model for network processors

  2004cited by this paper
• Optimization and benchmark of cryptographic algorithms on network processors

  2004cited by this paper
• NP-Click: a productive software development approach for network processors

  2004cited by this paper
• Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas

  2004cited by this paper
• Automated Task Allocation on Single Chip, Hardware Multithreaded, Multiprocessor Systems

  2004cited by this paper
• NP-Click: A Programming Model for the Intel IXP1200

  2004cited by this paper
• IXP2400/2800 Programming: The Complete Microengine Coding Guide

  2003cited by this paper
• Programming challenges in network processor deployment

  2003cited by this paper
• Creating advanced functions on network processors: experience and perspectives

  2003cited by this paper
• PacketBench: a tool for workload characterization of network processing

  2003cited by this paper
• Network Processor Design: Issues and Practices

  2002cited by this paper
• Network Processors: Origin of Species

  2002cited by this paper
• Design Space Exploration of Network Processor Architectures

  2002cited by this paper
• Readings in hardware / software co-design

  2001cited by this paper
• Beyond Moore's Law: Internet Growth Trends

  2000influential reference
• MILP based task mapping for heterogeneous multiprocessor systems

  1996cited by this paper
• Scheduling and Load Balancing in Parallel and Distributed Systems

  1995cited by this paper
• A formal approach to the scheduling problem in high level synthesis

  1991cited by this paper

• Policy Gradient-Based Core Placement Optimization for Multichip Many-Core Systems

  2021cites this paper
• Performance Evaluation of Application Mapping Approaches for Network-on-Chip Designs

  2020cites this paper
• Application-Specific SoC Design Using Core Mapping to 3D Mesh NoCs with Nonlinear Area Optimization and Simulated Annealing

  2020cites this paper
• Bandwidth-Constrained Multi-Objective Segmented Brute-Force Algorithm for Efficient Mapping of Embedded Applications on NoC Architecture

  2018cites this paper
• Optimal mapping of program overlays onto many-core platforms with limited memory capacity

  2017cites this paper
• An evaluation power model for TriBA based application mapping and memory-on-chip

  2017cites this paper
• Hardware-accelerated evolutionary hard real-time task mapping for wormhole network-on-chip with priority-preemptive arbitration

  2016cites this paper
• Communication-aware branch and bound with cluster-based latency-constraint mapping technique on network-on-chip

  2016cites this paper
• Cluster Based Application Mapping Strategy for 2D NoC

  2016cites this paper
• Automatic Parallelization of Multirate Block Diagrams of Control Systems on Multicore Platforms

  2016cites this paper
• A Automatic Parallelization of Multi-rate Simulink Control Models for Multi-core Architectures

  2016cites this paper
• RASMAP: An efficient heuristic application mapping algorithm for network-on-chips

  2016cites this paper
• Memory-Aware NoC Application Mapping Based on Adaptive Genetic Algorithm

  2015cites this paper
• Efficient Test Scheduling and IP Mapping Algorithm for NOC Based SOC

  2015cites this paper
• Automatic Parallelization of Simulink Models for Multi-core Architectures

  2015cites this paper
• Task mapping and mesh topology exploration for an FPGA-based network on chip

  2015cites this paper
• Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes

  2015cites this paper
• Application Mapping on Network-on-Chip

  2014cites this paper
• Application-Specific Heterogeneous Network-on-Chip Design

  2014cites this paper
• An Adaptive Genetic Algorithm for Mesh-Based NoC Application Mapping

  2014cites this paper
• NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

  2013cites this paper
• Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration

  2013cites this paper
• A survey on application mapping strategies for Network-on-Chip design

  2013cites this paper
• Performance-Aware Design Of Dynamically Reconfigurable System-On-Chips With Quality Of Service Guarantees

  2013cites this paper
• UNISM: Unified Scheduling and Mapping for General Networks on Chip

  2012cites this paper
• SmartMem: an advanced memory subsystem for networking applications

  2012cites this paper
• Efficient Scheduling Algorithms for MpSoC Systems

  2011cites this paper
• Combining process splitting and merging transformations for Polyhedral Process Networks

  2010cites this paper
• Multicore Architectures With Dynamically Reconfigurable Array Processors for Wireless Broadband Technologies

  2009cites this paper
• An ILP formulation for task mapping and scheduling on multi-core architectures

  2009cites this paper
• Mapping Parallel Workload onto Network Processors Using Simulated Annealing

  2008cites this paper
• SCALABLE COMPUTING Practice and Experience

  2008cites this paper
• Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer

  2008cites this paper
• Mapping task graphs onto Network Processors using genetic algorithm

  2008cites this paper
• Efficient Implementation of WiMAX Physical Layer on Multi-core Architectures with Dynamically Reconfigurable Processors

  2008cites this paper
• Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical Layer

  2008cites this paper
• ILP and heuristic techniques for system-level design on network processor architectures

  2007cites this paper