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Field-Programmable Gate Array Implementation of Backprojection Algorithm for Circular Synthetic Aperture Radar

Jinmoo Heo,Seongjoo Lee,Yunho Jung

Published 2025 in Electronics

ABSTRACT

This paper presents a backprojection algorithm (BPA) accelerator implemented on a field-programmable gate array (FPGA) for circular synthetic aperture radar (SAR) systems. Although the BPA offers superior image quality, it requires significantly more computation and is memory intensive, necessitating hardware optimization. In particular, the BPA accumulates image data, leading to high memory requirements that must be reduced for embedded system implementation. To address this issue, we optimized the floating-point (FP) bit width, focusing on the output data that form the image, rather than only reducing the internal computation bit widths as in previous studies. Specifically, we optimized the exponent and mantissa widths in six computational units, prioritizing memory optimization for image data before reducing the computational logic. The proposed BPA accelerator achieved a 77% reduction in memory usage and a 73–74% reduction in computational logic while maintaining an image quality with a structural similarity index measure (SSIM) of 0.99 or higher. These optimizations significantly enhanced the feasibility of BPA processing in embedded systems.

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