NC-ROLL-FIA: Negative Capacitance FET based designs for Robust Logic Locking against Fault Injection Attacks Enabling Trustworthy Hardware for Edge AI Devices

No abstract is available for this paper.

• Publication year

  2025

• Venue

  Results in Engineering

• Publication date

  2025-08-01

• Fields of study

  Not labeled

• Identifiers
  DOI 10.1016/j.rineng.2025.106962
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Insights Into Design Optimization of Negative Capacitance Complementary-FET (CFET)

  2025cited by this paper
• An Energy Efficient and DPA Attack Resilient NCFET-Based S-Box Design for Secure and Lightweight SLIM Ciphers

  2025cited by this paper
• Enhancing Security in On-Chip Communication: A Survey of Threats and Solutions

  2024cited by this paper
• Fully Hybrid TLSv1.3 in WolfSSL on Cortex-M4

  2024cited by this paper
• Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices

  2024cited by this paper
• Efficient and Side-Channel Resistant Ed25519 on ARM Cortex-M4

  2024cited by this paper
• Optimizing the Threshold Modified Comparator Circuit (TMCC) with NCFET Technology for Low Power and High-Speed Performance

  2024cited by this paper
• Computing in-memory reconfigurable (accurate/approximate) adder design with negative capacitance FET 6T-SRAM for energy efficient AI edge devices

  2024cited by this paper
• Current Prospects and Challenges in Negative-Capacitance Field-Effect Transistors

  2023cited by this paper
• A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks

  2023cited by this paper
• Error Detection Constructions for ITA Finite Field Inversions Over $\text{GF}(2^{m})$ on FPGA Using CRC and Hamming Codes

  2023cited by this paper
• A New Optimal Method for the Secure Design of Combinational Circuits against Hardware Trojans Using Interference Logic Locking

  2023cited by this paper
• Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design

  2023cited by this paper
• Negative capacitance FETs for energy efficient and hardware secure logic designs

  2022cited by this paper
• Advances in Logic Locking: Past, Present, and Prospects

  2022cited by this paper
• Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

  2021cited by this paper
• Fast Strategies for the Implementation of SIKE Round 3 on ARM Cortex-M4

  2021cited by this paper
• Back‐End CMOS Compatible and Flexible Ferroelectric Memories for Neuromorphic Computing and Adaptive Sensing

  2021cited by this paper
• High-Speed NTT-based Polynomial Multiplication Accelerator for Post-Quantum Cryptography

  2021cited by this paper
• Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits

  2021cited by this paper
• Attacks on Logic Locking Obfuscation Techniques

  2021cited by this paper
• Security Challenges in Hardware Used for Smart Environments

  2020cited by this paper
• Removal Attacks on Logic Locking and Camouflaging Techniques

  2020cited by this paper
• Design of an 45nm NCFET Based Compute-in-SRAM for Energy-Efficient Machine Learning Applications

  2020cited by this paper
• Optimized Architectures for Elliptic Curve Cryptography over Curve448

  2020cited by this paper
• Power-Efficient Heterogeneous Many-Core Design With NCFET Technology

  2020cited by this paper
• Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

  2020cited by this paper
• Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) – Unlocked

  2019cited by this paper
• Negative Capacitance FET With 1.8-nm-Thick Zr-Doped HfO2 Oxide

  2019cited by this paper
• Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances

  2019cited by this paper
• SFLL-HLS: Stripped-Functionality Logic Locking Meets High-Level Synthesis

  2019cited by this paper
• Design-for-Error-Detection in Implementations of Cryptographic Nonlinear Substitution Boxes Benchmarked on ASIC

  2018cited by this paper
• Ferroelectric Negative Capacitance Field Effect Transistor

  2018cited by this paper
• ATPG-based cost-effective, secure logic locking

  2018cited by this paper
• Reliable hardware architectures for efficient secure hash functions ECHO and fugue

  2018cited by this paper
• New Insights into the Physical Origin of Negative Capacitance and Hysteresis in NCFETs

  2018cited by this paper
• Work Function Engineering for Performance Improvement in Leaky Negative Capacitance FETs

  2017cited by this paper
• NCFET: Opportunities & challenges for advanced technology nodes

  2017cited by this paper
• Hardware Protection through Obfuscation

  2017cited by this paper
• Post-Quantum Cryptography on FPGA Based on Isogenies on Elliptic Curves

  2017cited by this paper
• Introduction to Hardware Obfuscation: Motivation, Methods and Evaluation

  2017cited by this paper
• Logic Locking Using Hybrid CMOS and Emerging SiNW FETs

  2017cited by this paper
• Weighted logic locking: A new approach for IC piracy protection

  2017cited by this paper
• Provably-Secure Logic Locking: From Theory To Practice

  2017cited by this paper
• Enabling Energy-Efficient Nonvolatile Computing With Negative Capacitance FET

  2017cited by this paper
• TTLock: Tenacious and traceless logic locking

  2017cited by this paper
• Design Space Exploration of Hysteresis-Free HfZrOx-Based Negative Capacitance FETs

  2017cited by this paper
• Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction

  2016cited by this paper
• Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part II: Model Validation

  2016cited by this paper
• Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

  2016cited by this paper
• Energy-Efficient Long-term Continuous Personal Health Monitoring

  2015cited by this paper
• Improving logic obfuscation via logic cone analysis

  2015cited by this paper
• Systematic Poisoning Attacks on and Defenses for Machine Learning in Healthcare

  2015cited by this paper
• A Primer on Hardware Security: Models, Methods, and Metrics

  2014cited by this paper
• A fault induction technique based on voltage underfeeding with application to attacks against AES and RSA

  2013cited by this paper
• Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation

  2011cited by this paper
• Introduction to Hardware Security and Trust

  2011cited by this paper
• Modeling and Design of Ferroelectric MOSFETs

  2011cited by this paper
• Low voltage fault attacks to AES

  2010cited by this paper
• Concurrent Structure-Independent Fault Detection Schemes for the Advanced Encryption Standard

  2010cited by this paper
• A low-cost S-box for the Advanced Encryption Standard using normal basis

  2009cited by this paper
• HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection

  2009cited by this paper
• IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

  2007cited by this paper
• Patents, software, and hardware for PID control: an overview and analysis of the current art

  2006cited by this paper
• Beyond CMOS

  2002cited by this paper
• Constraint-based watermarking techniques for design IP protection

  2001cited by this paper

• Adiabatic Logic-Based Lightweight Cryptography: A Low-Vt Charge-Balanced Symmetric Pre-Resolve Approach for Power Analysis Resistant PRESENT

  2026cites this paper