A 14 ns-Latency $9 \text{Gb}/\mathrm{s} 0.44 \text{mm}^{2} 62 \text{pJ}/\mathrm{b}$ Short-Blocklength LDPC Decoder ASIC in 22FDX

Ultra-reliable low latency communication (URLLC) is a key part of 5 G wireless systems. Achieving low latency necessitates codes with short blocklengths for which polar codes with successive cancellation list (SCL) decoding typically outperform message-passing (MP)-based decoding of low-density parity-check (LDPC) codes. However, SCL decoders are known to exhibit high latency and poor area efficiency. In this paper, we propose a new short-blocklength multi-rate binary LDPC code that outperforms the 5G-LDPC code for the same blocklength and is suitable for URLLC applications using fully parallel MP. To demonstrate our code's efficacy, we present a $\mathbf{0. 4 4} \mathbf{m m}^{2}$ GlobalFoundries 22FDX LDPC decoder ASIC which supports three rates and achieves the lowest-in-class decoding latency of 14 ns while reaching an information throughput of $9 ~\text{Gb} / \mathrm{s}$ at $62 \text{pJ} / \mathrm{b}$ energy efficiency for a rate- $\mathbf{1} \boldsymbol{/} \mathbf{2}$ code with $\mathbf{1 2 8}$-bit blocklength.

• Publication year

  2025

• Venue

  2025 IEEE European Solid-State Electronics Research Conference (ESSERC)

• Publication date

  2025-09-08

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/ESSERC66193.2025.11214109arXiv 2512.17834
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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