A Prototyping Framework for P4-Programmable Traffic Managers

Traffic managers in programmable networks remain rigid and un-derexplored due to the lack of prototyping tools that support rapid design iteration and runtime reconfigurability. This paper presents a novel architecture and prototyping methodology for a programmable scheduler, built around lightweight nodes interconnected via a Network-on-Chip (NoC). Each node embeds a 32-bit RISC-V processor and configurable scheduling logic, allowing dynamic real-time policy updates through hot-swappable instruction memory. Our approach spans multiple abstraction levels: at the behavioral level, we extend BMv2 with a P4 interface to prototype and test scheduling policies within programmable data planes, while a SystemC model deployed with High-Level Synthesis (HLS) supports hardware refinement and FPGA deployment. The architecture enables modular, scalable, and reconfigurable traffic management by decoupling scheduling logic from fixed RTL and centralized memory. This work lays the foundation for rapidly prototyping diverse scheduling policies and exploring hardware/software co-design for adaptive data plane systems.

• Publication year

  2025

• Venue

  RSP

• Publication date

  2025-09-28

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1145/3768617.3770728
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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