FPGA-Based Real-Time ISP Accelerator Using Low-Cost Line Buffers and Non-Linear Functions

In this paper, we present a resource-efficient image signal processing (ISP) accelerator for real-time mobile devices, with several optimization schemes for key building blocks such as denoising, demosaicing, and tone mapping. A novel buffer-matching method is adopted to minimize on-chip memory usage by adjusting the parallelism of each processing block. A resource-sharing method is employed to minimize resource consumption of the line-buffered pipelined hardware. Additionally, an efficient piecewise linear approximation is used to handle non-linear functions in the ISP stages, further reducing the computational costs. The implementation result on Xilinx XCVU19P FPGA shows that the proposed ISP accelerator achieves comparable image quality to the leading deep-learning-based solution while improving resource efficiency by up to 2.76x.

• Publication year

  2025

• Venue

  Asia Pacific Conference on Circuits and Systems

• Publication date

  2025-10-12

• Fields of study

  Not labeled

• Identifiers
  DOI 10.1109/APCCAS67402.2025.11377941
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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