Power-Optimized ALU Framework Based on Pseudo Dynamic Buffer Domino Logic

With the rapid scaling of CMOS technology, balancing high-speed performance with low-power consumption has emerged as one of the central challenges in modern VLSI design. Among the core digital components, the Arithmetic and Logic Unit (ALU) plays a crucial role in determining the efficiency and performance of the overall system. While conventional domino logic circuits are favoured for their speed and compact design, they often suffer from high switching activity and considerable leakage power, making them less suitable for low power applications. To overcome these limitations, this paper presents a semi-custom design of a 64-bit ALU based on Pseudo Dynamic Buffer (PDB) Domino Logic, implemented using Cadence Genus with 90nm CMOS technology. The ALU is designed to perform 16 operations—eight arithmetic and eight logical—and its performance is compared against a general ALU using conventional logic. The introduction of PDB logic significantly reduces unnecessary signal transitions, which in turn minimizes both dynamic and static power dissipation. The proposed design demonstrates superior energy efficiency with a 27.44% reduction in switching power and a remarkable 79.45% reduction in leakage power, demonstrating the superior energy efficiency of the proposed design. These results confirm that integrating PDB-based domino logic into ALU architecture provides an effective pathway toward achieving low-power digital processors for next-generation VLSI systems.

• Publication year

  2026

• Venue

  2026 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE)

• Publication date

  2026-01-22

• Fields of study

  Not labeled

• Identifiers
  DOI 10.1109/IITCEE67948.2026.11394168
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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