Low-Power FPGA Implementation of Spiking Neural Networks with Optimized Event-Based Encoding

Spiking Neural Networks (SNNs) offer energy-efficient, event-driven computation well-suited for embedded platforms. In this work, we present an end-to-end FPGA-based deployment for image classification using SNN and high-level synthesis (HLS). We introduce a novel encoding scheme that generates spikes in minimal timesteps without sacrificing accuracy. The deployment leverages ANN-to-SNN conversion to design hardware-efficient architectures for networks such as ResNet-8 and ResNet-20, while maintaining accuracy comparable to their ANN counterparts. On the CIFAR-10 dataset, our converted SNNs achieve accuracies of 88.01% and 91.96%, close to the original ANNs (88.95% and 92.43%). Importantly, the proposed design achieves substantial reductions in hardware resource utilization and power consumption (up to 3× lower power) compared to ANN implementations. These results demonstrate that our framework not only preserves classification accuracy but also enables resource-efficient, low-power deployment of SNNs on FPGAs.

• Publication year

  2025

• Venue

  International Conference on E-Business and E-Government

• Publication date

  2025-12-13

• Fields of study

  Not labeled

• Identifiers
  DOI 10.1109/icee67165.2025.11409777
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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