Clepsydra: Modeling timing flows in hardware designs

No abstract is available for this paper.

• Publication year

  2017

• Venue

  2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

• Publication date

  2017-11-13

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/ICCAD.2017.8203772
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Register transfer level information flow tracking for provably secure hardware design

  2017cited by this paper
• Imprecise security: Quality and complexity tradeoffs for hardware information flow tracking

  2016cited by this paper
• A Hardware Design Language for Timing-Sensitive Information-Flow Security

  2015cited by this paper
• On Subnormal Floating Point and Abnormal Timing

  2015cited by this paper
• Toward automatic proof generation for information flow policies in third-party hardware IP

  2015cited by this paper
• Leveraging Gate-Level Properties to Identify Hardware Timing Channels

  2014influential reference
• Sapper: a language for hardware-level security policy enforcement

  2014cited by this paper
• Proof carrying-based information flow tracking for data secrecy protection and hardware trust

  2012cited by this paper
• Caisson: a hardware description language for secure information flow

  2011cited by this paper
• Crafting a usable microkernel, processor, and I/O system with strict and provable information flow security

  2011cited by this paper
• Information flow isolation in I2C and USB

  2011cited by this paper
• Complete information flow tracking from the gates up

  2009influential reference
• Cheap Hardware Parallelism Implies Cheap Security

  2007cited by this paper
• New cache designs for thwarting software cache-based side channel attacks

  2007cited by this paper
• Tate Pairing with Strong Fault Resiliency

  2007cited by this paper
• Fault Diagnosis and Tolerance in Cryptography

  2006cited by this paper
• Cache-timing attacks on AES

  2005influential reference
• CACHE MISSING FOR FUN AND PROFIT

  2005cited by this paper
• A Timing Attack against RSA with the Chinese Remainder Theorem

  2000cited by this paper
• Timing Attacks on Implementations of Di(cid:14)e-Hellman, RSA, DSS, and Other Systems

  1996cited by this paper
• Reducing timing channels with fuzzy time

  1991cited by this paper

• SHIFT: Selective Hardware Information Flow Tracking Driven by Deterministic Constraints

  2025cites this paper
• FeedbackFuzz: Fuzzing Processors via Intricate Program Generation with Feedback Engine

  2025cites this paper
• SymbFuzz: Symbolic Execution Guided Hardware Fuzzing

  2025cites this paper
• Leveraging the Benefits of Information Flow Tracking for Detecting Hardware Design Flaws

  2025cites this paper
• FastPath: A Hybrid Approach for Efficient Hardware Security Verification

  2025cites this paper
• Hardware Hybrid Testing Technology Based on Information Flow Path Guidance

  2025cites this paper
• RTL Verification for Secure Speculation Using Contract Shadow Logic

  2024cites this paper
• HybriDIFT: Scalable Memory-Aware Dynamic Information Flow Tracking for Hardware

  2024cites this paper
• μCFI: Formal Verification of Microarchitectural Control-flow Integrity

  2024cites this paper
• Exploring Coverage Metrics in Hardware Fuzzing: A Comprehensive Analysis

  2024cites this paper
• Data-Oblivious and Performant: On Designing Security-Conscious Hardware

  2024cites this paper
• SEIF: Augmented Symbolic Execution for Information Flow in Hardware Designs

  2023cites this paper
• SpecVerilog: Adapting Information Flow Control for Secure Speculation

  2023cites this paper
• Hardware/software security co-verification and vulnerability detection: An information flow perspective

  2023cites this paper
• Security Verification of Low-Trust Architectures

  2023cites this paper
• A Scalable Formal Verification Methodology for Data-Oblivious Hardware

  2023cites this paper
• Sylvia: Countering the Path Explosion Problem in the Symbolic Execution of Hardware Designs

  2023cites this paper
• Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance

  2023cites this paper
• Challenges and Opportunities of Security-Aware EDA

  2022influential citation
• TheHuzz: Instruction Fuzzing of Processors Using Golden-Reference Models for Finding Software-Exploitable Vulnerabilities

  2022cites this paper
• Efficient Method for Timing-based Information Flow Verification in Hardware Designs

  2022influential citation
• ATLaS: Automatic Detection of Timing-based Information Leakage Flows for SystemC HLS Designs

  2021cites this paper
• Integrating Information Flow Tracking into High-Level Synthesis Design Flow

  2021cites this paper
• Early Validation of SoCs Security Architecture Against Timing Flows Using SystemC-based VPs

  2021cites this paper
• Isadora: Automated Information Flow Property Generation for Hardware Designs

  2021cites this paper
• A Methodology For Creating Information Flow Specifications of Hardware Designs

  2021cites this paper
• Proof-Carrying Hardware-Based Information Flow Tracking in Analog/Mixed-Signal Designs

  2021cites this paper
• An Overview of Hardware Security and Trust: Threats, Countermeasures, and Design Tools

  2021cites this paper
• Hardware Information Flow Tracking

  2021influential citation
• A formal model for proving hardware timing properties and identifying timing channels

  2020cites this paper
• A review of hardware timing channel detection and mitigation

  2020cites this paper
• Transys: Leveraging Common Security Properties Across Hardware Designs

  2020cites this paper
• A Noval Method of Security Verification for JTAG Protection Function

  2019cites this paper
• VeriSketch: Synthesizing Secure Hardware Designs with Timing-Sensitive Information Flow Properties

  2019cites this paper
• Property Specific Information Flow Analysis for Hardware Security Verification

  2018cites this paper
• Processor Hardware Security Vulnerabilities and their Detection by Unique Program Execution Checking

  2018cites this paper
• When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs

  2018cites this paper
• Identifying and Measuring Security Critical Path for Uncovering Circuit Vulnerabilities

  2017influential citation