Optimized design of full-subtractor using new SRG reversible logic gates and VHDL simulation

No abstract is available for this paper.

• Publication year

  2015

• Venue

  International Conference on E-Learning and E-Technologies in Education

• Publication date

  2015-11-01

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/CEEE.2015.7428295
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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