Generating FPGA-Accelerated DFT Libraries

No abstract is available for this paper.

• Publication year

  2007

• Venue

  IEEE Symposium on Field-Programmable Custom Computing Machines

• Publication date

  Unknown publication date

• Fields of study

  Not labeled

• Identifiers

  No identifiers available.

• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Performance/Energy Optimization of DSP Transforms on the XScale Processor

  2007cited by this paper
• Discrete Fourier Transform Compiler : From Mathematical Representation to Efficient Hardware

  2007influential reference
• IMPROVEMENTS OF THE GCLP ALGORITHM FOR HW / SW PARTITIONING OF TASK GRAPHS

  2006cited by this paper
• Fast and accurate resource estimation of automatically generated custom DFT IP cores

  2006cited by this paper
• Image Processing Application Development: From Rapid Prototyping to SW/HW Co-simulation and Automated Code Generation

  2005cited by this paper
• Formal loop merging for signal transforms

  2005cited by this paper
• Algorithmic aspects of hardware/software partitioning

  2005cited by this paper
• A Scalable Embedded JPEG2000 Architecture

  2005cited by this paper
• Automatic generation of customized discrete Fourier transform IPs

  2005influential reference
• SPIRAL: Code Generation for DSP Transforms

  2005influential reference
• In handbook of automated reasoning

  2001cited by this paper
• Exploiting FPGA-features during the emulation of a fast reactive embedded system

  1999cited by this paper
• SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design

  1998cited by this paper
• Garp: a MIPS processor with a reconfigurable coprocessor

  1997cited by this paper
• A global criticality/local phase driven algorithm for the constrained hardware/software partitioning problem

  1994cited by this paper
• A simple fixed-point error bound for the fast Fourier transform

  1979influential reference
• A fixed-point fast Fourier transform error analysis

  1969influential reference

• Towards An Approach to Identify Divergences in Hardware Designs for HPC Workloads

  2025cites this paper
• Fully Integrated FPGA Molecular Dynamics Simulations

  2019cites this paper
• Real-time 20.37 Gb/s optical OFDM receiver for PON IM/DD systems.

  2018cites this paper
• GapFlyt: Active Vision Based Minimalist Structure-Less Gap Detection For Quadrotor Flight

  2018cites this paper
• Towards Efficient Hardware Acceleration of Deep Neural Networks on FPGA

  2018cites this paper
• SPIRAL: Extreme Performance Portability

  2018influential citation
• Image Reconstruction Using Novel Two-Dimensional Fourier Transform

  2018cites this paper
• Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?

  2017cites this paper
• Asynchronous Event-Based Fourier Analysis

  2017cites this paper
• Staging for generic programming in space and time

  2017cites this paper
• A Low Cost Structurally Optimized Design for Diverse Filter Types

  2016cites this paper
• Design and Modeling of Specialized Architectures

  2016cites this paper
• A transformation-based approach to hardware design using higher-order functions

  2015cites this paper
• 2D Discrete Fourier Transform with simultaneous edge artifact removal for real-time applications

  2015cites this paper
• A review on methods, issues and challenges in neuromorphic engineering

  2015cites this paper
• 3D FFTs on a Single FPGA

  2014cites this paper
• 3D FFT for FPGAs

  2013cites this paper
• Exploring the latency-resource trade-off for the Discrete Fourier Transform on the FPGA

  2012cites this paper
• A fixed point of DFT/FFT for FPGA platform

  2012cites this paper
• A parallel processing framework for spectral based computations

  2012cites this paper
• Avoiding game over: Bringing design to the next level

  2012cites this paper
• Domain-Specific Optimization of Signal Recognition Targeting FPGAs

  2011cites this paper
• Automatic IP Generation of FFT/IFFT Processors with Word-Length Optimization for MIMO-OFDM Systems

  2011cites this paper
• Floating-point mixed-radix FFT core generation for FPGA and comparison with GPU and CPU

  2011cites this paper
• Multidimensional DFT IP Generator for FPGA Platforms

  2011cites this paper
• Integrated circuits towards reducing e-waste: Future design directions

  2010cites this paper
• A mathematical approach for compiling and optimizing hardware implementation of DSP transforms

  2010cites this paper
• Hardware and software infrastructure for a family of floating-gate based FPAAs

  2010cites this paper
• Accelerating 2D FFT with Non-Power-of-Two Problem Size on FPGA

  2010cites this paper
• Computation reuse in domain-specific optimization of signal recognition

  2009cites this paper
• Net-Sensitivity-Based Optimization of Large-Scale Field-Programmable Analog Array (FPAA) Placement and Routing

  2009cites this paper
• Psychoacoustic bass enhancement system on reconfigurable analog signal processor

  2009cites this paper
• FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

  2009cites this paper
• Use Object-Oriented Platform to Facilitate FPGA-Based Computing in Embedded Systems

  2009cites this paper
• An Efficient Power-Aware Resource Scheduling Strategy in Virtualized Datacenters

  2009cites this paper
• Library generation for linear transforms

  2008cites this paper
• An efficient implementation of a phase unwrapping kernel on reconfigurable hardware

  2008cites this paper
• Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison

  2008cites this paper
• Automated conversion of Simulink designs to analog hardware on an FPAA

  2008cites this paper
• Phase unwrapping on reconfigurable hardware and graphics processors

  2008cites this paper
• Domain-specific library generation for parallel software and hardware platforms

  2008cites this paper