This article introduces a combinatorial optimization approach to register allocation and instruction scheduling, two central compiler problems. Combinatorial optimization has the potential to solve these problems optimally and to exploit processor-specific features readily. Our approach is the first to leverage this potential in practice: it captures the complete set of program transformations used in state-of-the-art compilers, scales to medium-sized functions of up to 1,000 instructions, and generates executable code. This level of practicality is reached by using constraint programming, a particularly suitable combinatorial optimization technique. Unison, the implementation of our approach, is open source, used in industry, and integrated with the LLVM toolchain. An extensive evaluation confirms that Unison generates better code than LLVM while scaling to medium-sized functions. The evaluation uses systematically selected benchmarks from MediaBench and SPEC CPU2006 and different processor architectures (Hexagon, ARM, MIPS). Mean estimated speedup ranges from 1.1% to 10% and mean code size reduction ranges from 1.3% to 3.8% for the different architectures. A significant part of this improvement is due to the integrated nature of the approach. Executing the generated code on Hexagon confirms that the estimated speedup results in actual speedup. Given a fixed time limit, Unison solves optimally functions of up to 946 instructions, nearly an order of magnitude larger than previous approaches. The results show that our combinatorial approach can be applied in practice to trade compilation time for code quality beyond the usual compiler optimization levels, identify improvement opportunities in heuristic algorithms, and fully exploit processor-specific features.
Combinatorial Register Allocation and Instruction Scheduling
Roberto Castañeda Lozano,M. Carlsson,Gabriel Hjort Blindell,Christian Schulte
Published 2018 in ACM Transactions on Programming Languages and Systems
ABSTRACT
PUBLICATION RECORD
- Publication year
2018
- Venue
ACM Transactions on Programming Languages and Systems
- Publication date
2018-04-06
- Fields of study
Computer Science
- Identifiers
- External record
- Source metadata
Semantic Scholar
CITATION MAP
EXTRACTION MAP
CLAIMS
CONCEPTS
- arm
A target processor architecture used in the evaluation.
- combinatorial optimization
An optimization paradigm that searches a discrete solution space under formal constraints and objective criteria.
- constraint programming
A combinatorial optimization technique that models decisions as variables subject to constraints.
- executable code
Machine code produced by the compiler optimization workflow and intended to run on a target processor.
- fixed time limit
A bounded solving budget used to measure how much of a function can be optimized optimally.
- hexagon
A target processor architecture used in the evaluation and execution tests.
- instruction scheduling
The compiler problem of ordering instructions while respecting dependencies and resource constraints.
- llvm toolchain
The LLVM compiler infrastructure used as the integration and comparison environment.
Aliases: LLVM
- mediabench
A benchmark suite used to evaluate the generated code quality and scalability.
- medium-sized functions
Functions in the size range targeted by the approach, up to about 1,000 instructions.
- mips
A target processor architecture used in the evaluation.
- register allocation
The compiler problem of assigning program values to machine registers during code generation.
- spec cpu2006
A CPU benchmark suite used alongside MediaBench for evaluation.
- unison
The implementation of the proposed combinatorial compiler optimization approach.
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