New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

We have developed 3rd generation DRP, dynamically reconfigurable processor, for accelerating deep neural networks (DNNs) in embedded micro-processor systems. A DRP unit (supporting 16b FP from this generation) and a newly designed multiply-and-accumulate (MAC) unit are tightly integrated into an STP-3 AI core to achieve high versatility, high performance, and low latency DNN processing. The core also features narrow bit-width streaming data exchange mechanism between the two units. Not only basic 16b FP but also binarized DNN inference computations are supported.

• Publication year

  2018

• Venue

  2018 IEEE Symposium on VLSI Circuits

• Publication date

  2018-06-01

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/VLSIC.2018.8502438
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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