Low Power Design on Algorithmic and Architectural Level: A Case Study of an HSDPA Baseband Digital Signal Processing System

No abstract is available for this paper.

• Publication year

  2007

• Venue

  2007 Design, Automation & Test in Europe Conference & Exhibition

• Publication date

  2007-04-16

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/DATE.2007.364495
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Power optimization of digital baseband WCDMA receiver components on algorithmic and architectural level

  2008influential reference
• Channel Equalization in HSDPA Receivers: Trade-Off between Performance and Complexity with a Variable Oversampling

  2006cited by this paper
• Low power VLSI architecture for adaptive MAI suppression in CDMA using multi-stage convergence masking vector

  2005cited by this paper
• Low-Power Electronics Design

  2004cited by this paper
• A parametric error analysis of Goldschmidt's division algorithm

  2003cited by this paper
• EURASIP Journal on Applied Signal Processing 2002:8, 757–770 c ○ 2002 Hindawi Publishing Corporation Chip-Level Channel Equalization in WCDMA Downlink

  2002cited by this paper
• A novel blind adaptive algorithm for channel equalization in WCDMA downlink

  2002cited by this paper
• Simple MMSE equalizers for CDMA downlink to restore chip sequence: comparison to zero-forcing and RAKE

  2000cited by this paper
• Mathematical Methods and Algorithms for Signal Processing

  1999cited by this paper
• Multiuser detection:

  1999cited by this paper
• Low-Power CMOS Wireless Communications

  1998cited by this paper
• High-Level Power Analysis and Optimization

  1997cited by this paper
• Low-Power CMOS Wireless Communications: A Wideband CDMA System Design

  1997cited by this paper
• Adaptive Signal Processing

  1991cited by this paper
• Efficient complex matrix multiplication

  1988cited by this paper

• On the Design of a Suitable Hardware Platform for Protocol Stack Processing in LTE Terminals

  2009cites this paper