VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors

No abstract is available for this paper.

• Publication year

  2007

• Venue

  International Workshop on Arithmetic of Finite Fields

• Publication date

  2007-06-21

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1007/978-3-540-73074-3_5
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Cryptographic Hardware and Embedded Systems - CHES 2006, 8th International Workshop, Yokohama, Japan, October 10-13, 2006, Proceedings

  2006cited by this paper
• Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors

  2006influential reference
• Speeding Up AES By Extending a 32 bit Processor Instruction Set

  2006cited by this paper
• Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography

  2005cited by this paper
• Computational Science and Its Applications - ICCSA 2005, International Conference, Singapore, May 9-12, 2005, Proceedings, Part I

  2005cited by this paper
• Cryptography: circuits and systems approach

  2005cited by this paper
• An Instruction Set Extension for Fast and Memory-Efficient AES Implementation

  2005cited by this paper
• Embedded software integration for coarse-grain reconfigurable systems

  2004cited by this paper
• Interfacing a high speed crypto accelerator to an embedded CPU

  2004influential reference
• Extended instructions for the AES cryptography and their efficient implementation

  2004cited by this paper
• Low-Power Design of a Functional Unit for Arithmetic in Finite Fields GF ( p ) and GF ( 2 m )

  2003influential reference
• Subword parallel GF(2/sup m/) ALU: an implementation for a cryptographic processor

  2003cited by this paper
• Cryptographic Hardware and Embedded Systems — CHES 2000

  2002cited by this paper
• The Design of Rijndael

  2002cited by this paper
• Efficient Software Implementation of AES on 32-Bit Platforms

  2002cited by this paper
• Theoretical Use of Cache Memory as a Cryptanalytic Side-Channel

  2002cited by this paper
• The Design of Rijndael: AES - The Advanced Encryption Standard

  2002influential reference
• A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)

  2000cited by this paper
• The State of Elliptic Curve Cryptography

  2000influential reference

• A hardware-software co-designed AES-ECC cryptosystem

  2017cites this paper
• Instruction set extensions of AES algorithms for 32-bit processors

  2014cites this paper
• FPGA based unified architecture for public key and private key cryptosystems

  2013cites this paper
• Secure outsourced computation of iris matching

  2012cites this paper
• A Hardware Processor Supporting Elliptic Curve Cryptography for Less than 9 kGEs

  2011cites this paper
• A Unified Architecture for Supporting Operations of AES and ECC

  2011cites this paper
• Boosting AES Performance on a Tiny Processor Core

  2008cites this paper
• Specification of Secure Instruction Sets for EP 2 P Devices

  2007cites this paper