Delay-Tolerant Wireless Networks on Chip: Preliminary Analysis and Results

Delay Tolerant Networks (DTNs) are designed to be robust against delays and disruptions of any kind. Indeed, any failure in a set of DTN nodes can be mapped into a delay and thus, can be properly tolerated and counteracted. In general, DTN are applied to scenarios with relative long distances and link interruption between the nodes. In this work, we propose to study DTN operating on distances between nodes several orders of minor magnitude: a wireless DTN on a chip level. The term DTNOC is thus coined to describe DTN applied on a chip scale, where delays and time intervals are reduced accordingly the new application domain. This paper presents the main advantages and characteristics of DTNOCs while discussing up to which point DTNOCs inherit original DTN properties and functions. A preliminary case study is presented and analyzed. Obtained results encourages the future research and development of DTNOCs.

• Publication year

  2019

• Venue

  Latin American Test Symposium

• Publication date

  2019-03-11

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/LATW.2019.8704623
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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