Buffer insertion for noise and delay optimization

No abstract is available for this paper.

• Publication year

  1998

• Venue

  Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

• Publication date

  1998-05-01

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1145/277044.277145
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response

  1998cited by this paper
• PRIMO: probability interpretation of moments for delay calculation

  1998cited by this paper
• Analysis, reduction and avoidance of crosstalk on VLSI chips

  1998cited by this paper
• Timing Optimization For Multi-source Nets: Characterization And Optimal Repeater Insertion

  1997cited by this paper
• Crosstalk reduction for VLSI

  1997cited by this paper
• Efficient coupled noise estimation for on-chip interconnects

  1997influential reference
• Wire Segmenting For Improved Buffer Insertion

  1997influential reference
• Delay bounded buffered tree construction for timing driven floorplanning

  1997cited by this paper
• Closed form solution to simultaneous buffer insertion/sizing and wire sizing

  1997cited by this paper
• A new approach to simultaneous buffer insertion and wire sizing

  1997cited by this paper
• Simultaneous routing and buffer insertion for high performance interconnect

  1996cited by this paper
• Interconnect Layout Optimization by Simultaneous Steiner Tree Construction and Buffer Insertion

  1996influential reference
• Performance optimization of VLSI interconnect layout

  1996cited by this paper
• Noise in deep submicron digital design

  1996cited by this paper
• Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm

  1995cited by this paper
• Optimal wire sizing and buffer insertion for low power and a generalized delay model

  1995influential reference
• On-chip cross talk-the new signal integrity challenge

  1995cited by this paper
• Techniques For Crosstalk Avoidance In The Physical Design Of High-performance Digital Systems

  1994cited by this paper
• RICE: rapid interconnect circuit evaluation using AWE

  1994cited by this paper
• A Methodology and Algorithms for Post-Placement Delay Optimization

  1994cited by this paper
• Optimum buffer circuits for driving long uniform lines

  1991cited by this paper
• A fast and efficient algorithm for determining fanout trees in large networks

  1991cited by this paper
• Circuits, interconnections, and packaging for VLSI

  1990cited by this paper
• Asymptotic waveform evaluation for timing analysis

  1990cited by this paper
• Buffer placement in distributed RC-tree networks for minimal Elmore delay

  1990cited by this paper
• The fanout problem: from theory to practice

  1989cited by this paper
• Microelectronics Packaging Handbook

  1988cited by this paper
• Signal delay in RC tree networks

  1983cited by this paper
• Signal Delay in RC Tree Networks

  1981cited by this paper
• Crosstalk (Noise) in Digital Systems

  1967cited by this paper
• The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers

  1948cited by this paper

• Performance-aware routing optimization for graphene nanoribbon interconnects

  2025cites this paper
• Differentiable Physical Optimization

  2025cites this paper
• Reducing delay and resistance of GNR based interconnect using insertion of buffers

  2025cites this paper
• AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL

  2024cites this paper
• Novel Tee-Shaped Topology Theory of Low- and High-Pass NGD Double-Type Function

  2022cites this paper
• High Performance Buffer with Body Biasing Technique

  2021cites this paper
• Crosstalk noise analysis in ternary logic multilayer graphene nanoribbon interconnects using shielding techniques

  2020cites this paper
• Routing-Free Crosstalk Prediction

  2020cites this paper
• Optimal memory utilization and wire length minimization for reducing energy consumption of VLSI circuits

  2019cites this paper
• Crosstalk Aware Global Routing of Graphene Nanoribbon Based Circuits

  2019cites this paper
• Buffer insertion for delay minimization in RLC interconnects using cuckoo optimization algorithm

  2018cites this paper
• Comprehensive Evaluation of Crosstalk and Delay Profiles in VLSI Interconnect Structures with Partially Coupled Lines

  2018cites this paper
• Optimization of Digital Circuits with Consideration of DF

  2018cites this paper
• Optimization Techniques for CNT Based VLSI Interconnects - A Review

  2017cites this paper
• High-speed and low-power repeater for VLSI interconnects

  2017cites this paper
• Obstacle aware delay optimized rectilinear steiner minimum tree routing

  2017cites this paper
• A CPS framework based perturbation constrained buffer planning approach in VLSI design

  2017cites this paper
• Technology-Dependent Logic Optimization The survey paper presents the state-of-the-art algorithms for technology-dependent optimizations, along with a comparison of their relative power to optimize the implementations of logic circuits.

  2015cites this paper
• A distinctive O(mn) time algorithm for optimal buffer insertions

  2015cites this paper
• Scaling Dependent Electrical Modeling of Interconnects

  2015cites this paper
• Mitigation of thermally induced crosstalk noise by dynamically adjusting driver strength

  2015cites this paper
• A Compact Low Power High Frequency Pulse Generator

  2015cites this paper
• Buffer Insertion as a Solution to Interconnect Issues

  2015cites this paper
• Smart and efficient multi-scenario SoC timing closure and ECO generator

  2015cites this paper
• Technology-Dependent Logic Optimization

  2015cites this paper
• Revisiting performance of various delay elements to realize a trigger pulse generator

  2015cites this paper
• Design Intelligence for Interconnection Realization in Power-Managed SoCs

  2015cites this paper
• Buffer Insertion for Delay Minimization using An Improved PSO Algorithm

  2014cites this paper
• Robust Design of CNFET Based Buffered Delay Model and Microwave Pulse Generator

  2014cites this paper
• Low-power delay buffer design using Asymmetric C-element gated clock strategy

  2014cites this paper
• Crosstalk-Aware Multiple Error Detection Scheme Based on Two-Dimensional Parities for Energy Efficient Network on Chip

  2014cites this paper
• Noise-Aware Power Optimization Technique for MTCMOS Circuits

  2014cites this paper
• An optimization algorithm for simultaneous routing and buffer insertion with delay-power constraints in VLSI layout design

  2014cites this paper
• Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning

  2013cites this paper
• MIRIM: Modified Interleaved Repeater Insertion Methodology to Reduce Delay Uncertainty in Global Interconnections

  2013cites this paper
• Construction of rectilinear Steiner minimum trees with slew constraints over obstacles

  2012cites this paper
• Test Pattern Generation for Multiple Aggressor Crosstalk Effects Considering Gate Leakage Loading in Presence of Gate Delays

  2012cites this paper
• Solutions to Improve the Reliability of On-Chip Interconnects

  2012cites this paper
• Communication Reliability in Network on Chip Designs

  2012cites this paper
• Aging Analysis of Digital Integrated Circuits

  2012cites this paper
• Crosstalk in VLSI partially coupled interconnect structures, a comprehensive evaluation

  2011cites this paper
• Switching Noise and Timing and Characteristics in Nanoscale Integrated Circuits

  2011cites this paper
• Multilayer Modeling and Design of Energy Managed Microsystems

  2011cites this paper
• Path aware event scheduler in HoldAdvisor for fixing min timing violations

  2011cites this paper
• Shedding Physical Synthesis Area Bloat

  2011cites this paper
• A comprehensive evaluation of crosstalk noise in partially coupled nano scale VLSI interconnects

  2011cites this paper
• Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs

  2011cites this paper
• Crosstalk aware coupled line delay tree construction for on-chip interconnects

  2011cites this paper
• Resource allocation in multi-project environments: Planning vs. execution strategies

  2011cites this paper
• A Data Capturing Method for Buses on Chip

  2010cites this paper
• Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus

  2009cites this paper
• A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion

  2009cites this paper
• Physical synthesis for nanometer VLSI and emerging technologies

  2008cites this paper
• Synthesis of On-Chip Communication Architectures

  2008cites this paper
• High-Level Synthesis Framework for Crosstalk Minimization in VLSI ASICs

  2008cites this paper
• An Efficient Method to Estimate Crosstalk after Placement Incorporating a Reduction Scheme

  2008cites this paper
• Algorithmic techniques for nanometer VLSI design and manufacturing closure

  2008cites this paper
• A practical repeater insertion flow

  2008cites this paper
• On-Chip Communication Architectures: System on Chip Interconnect

  2008cites this paper
• Reducing Interconnect Delay Uncertainty via Hybrid Polarity Repeater Insertion

  2008cites this paper
• On-chip crosstalk noise reduction model using interconnect optimization techniques

  2008cites this paper
• Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

  2008cites this paper
• A High-Performance Bus Architecture for Strongly Coupled Interconnects

  2008cites this paper
• Efficient crosstalk estimation and reduction in high speed designs

  2008cites this paper
• Proposing an efficient method to estimate and reduce crosstalk after placement in VLSI circuits

  2008cites this paper
• Test pattern generation for worst-case crosstalk faults in DSM chips using Genetic Algorithm

  2008cites this paper
• Performance and power optimization in VLSI physical design

  2008cites this paper
• Dual-$V_{dd}$ Buffer Insertion for Power Reduction

  2008cites this paper
• An efficient net ordering algorithm for buffer insertion

  2007cites this paper
• Simultaneous shield and buffer insertion for crosstalk noise reduction in global routing

  2007cites this paper
• Algorithms for the scaling toward nanometer VLSI physical synthesis

  2007cites this paper
• Techniques for Fast Physical Synthesis

  2007cites this paper
• Chapter 26 Buffer Insertion Basics

  2007cites this paper
• Path-Based Buffer Insertion

  2007cites this paper
• Asymmetric clock driver for improved power and noise performances

  2007cites this paper
• Variability-Aware VLSI Design Automation For Nanoscale Technologies

  2007cites this paper
• Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion

  2007cites this paper
• Glitch Control with Dynamic Receiver Threshold Adjustment

  2007cites this paper
• Analyzing the risk of timing modeling based on path delay tests.

  2007cites this paper
• Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip Interconnects

  2007cites this paper
• An Efficient Analytical Approach to Path-Based Buffer Insertion

  2007cites this paper
• A New Twisted Differential Line Structure in Global Bus Design

  2007cites this paper
• Fast Crosstalk Repair by Quick Timing Change Estimation

  2007cites this paper
• Fast Algorithms for Slew-Constrained Minimum Cost Buffering

  2007cites this paper
• Techniques for Fast Physical Synthesis Fast, efficient buffer design, logic transformations, and clustering components for placement are some of the techniques being used to reduce design turnaround for large, complex chips.

  2007cites this paper
• Crosstalk and delay optimization techniques for nano scale interconnects

  2007cites this paper
• Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits

  2007cites this paper
• Gate-size optimization under timing constraints for coupling-noise reduction

  2006cites this paper
• An O(mn) time algorithm for optimal buffer insertion of nets with m sinks

  2006cites this paper
• Low-Power Repeater Insertion for Global Interconnects

  2006cites this paper
• Latency-Guided On-Chip Bus-Network Design

  2006cites this paper
• On-Chip Networks Modeling and Simulation

  2006cites this paper
• Reliable crosstalk-driven interconnect optimization

  2006cites this paper
• Using Essential Inverters for Interconnect Delay Reduction

  2006cites this paper
• An Efficient Low-Power Repeater-Insertion Scheme

  2006cites this paper
• Convertisseur analogique/numérique pour un capteur à pixels actifs

  2006cites this paper
• Low-power repeater insertion with both delay and slew rate constraints

  2006cites this paper
• Logic Gates as Repeaters (LGR) for Area-Efficient Timing Optimization

  2006cites this paper
• An effective technique for simultaneous interconnect channel delay and noise reduction in nanometer VLSI design

  2006cites this paper
• Analysis and optimization under crosstalk and variability in deep sub-micron vlsi circuits

  2006cites this paper