Global Register Allocation Based on Graph Fusion

No abstract is available for this paper.

• Publication year

  1996

• Venue

  International Workshop on Languages and Compilers for Parallel Computing

• Publication date

  1996-08-08

• Fields of study

  Computer Science

• Identifiers
  DOI 10.1007/BFb0017257
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Register Allocation via Hierarchical Graph Coloring

  1996cited by this paper
• Region-based compilation: an introduction and motivation

  1995cited by this paper
• Zero-cost range splitting

  1994cited by this paper
• Register allocation over the program dependence graph

  1994influential reference
• Load/store range analysis for global register allocation

  1993cited by this paper
• Predicting conditional branch directions from previous runs of a program

  1992cited by this paper
• Register allocation via hierarchical graph coloring

  1991influential reference
• IMPACT: an architectural framework for multiple-instruction-issue processors

  1991cited by this paper
• Phase Ordering of Register Allocation and Instruction Scheduling

  1991influential reference
• The priority-based coloring approach to register allocation

  1990influential reference
• Spill code minimization techniques for optimizing compliers

  1989cited by this paper
• Spill Code Minimization Techniques for Optimizing Compilers

  1989cited by this paper
• Coloring heuristics for register allocation

  1989cited by this paper
• Effectiveness of a machine-level, global optimizer

  1986cited by this paper
• Register allocation via graph coloring

  1981influential reference
• Register Allocation Via Coloring

  1981influential reference

• Parallel trace register allocation

  2018cites this paper
• Trace-based Register Allocation in a JIT Compiler

  2016cites this paper
• A Máquina Virtual Java e a Otimização Inline: Um Estudo de Caso

  2012cites this paper
• A Framework for End-to-End Verification and Evaluation of Register Allocators

  2007cites this paper
• Compiler Optimizations for Multithreaded Multicore Network Processors

  2006cites this paper
• Lecture Notes in Computer Science: Preface

  2005cites this paper
• A Framework for End-to-End Evaluation of Register Allocators

  2005cites this paper
• Bit-level and packet-level, or Pollaczec-Khintchine formulae revisited

  2004cites this paper
• Genetic instruction scheduling and register allocation

  2004cites this paper
• Engineering a Compiler

  2003cites this paper
• Spill code minimization by spill code motion

  2003influential citation
• Efficient global register allocation for minimizing energy consumption

  2002cites this paper
• A faster optimal register allocator

  2002cites this paper
• Preference-directed graph coloring

  2002cites this paper
• Optimal spilling for CISC machines with few registers

  2001cites this paper
• Optimal Spilling for CISC Machines with Few

  2000cites this paper
• Fusion-based register allocation

  2000cites this paper
• C and tcc

  1999cites this paper
• Low energy register allocation beyond basic blocks

  1999cites this paper
• Optimistic register coalescing

  1998cites this paper
• Fast, effective code generation in a just-in-time Java compiler

  1998cites this paper
• tcc: a system for fast, flexible, and high-level dynamic code generation

  1997cites this paper
• Call-cost directed register allocation

  1997cites this paper
• Source-level debugging of globally optimized code

  1996cites this paper
• Code reuse in an optimizing compiler

  1996influential citation