Low-cost scan-based delay testing of latch-based circuits with time borrowing

No abstract is available for this paper.

• Publication year

  2006

• Venue

  IEEE VLSI Test Symposium

• Publication date

  2006-04-30

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/VTS.2006.45
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• 1 Structural Delay Testing Under Restricted Scan of Latch-based Pipelines with Time Borrowing

  2005influential reference
• Structural delay testing of latch-based high-speed pipelines with time borrowing

  2003influential reference
• Test generation for path-delay faults in one-dimensional iterative logic arrays

  2000cited by this paper
• High quality robust tests for path delay faults

  1997cited by this paper
• DYNAMITE: an efficient automatic test pattern generation system for path delay faults

  1991cited by this paper
• The BALLAST Methodology for Structured Partial Scan Design

  1990cited by this paper
• On Delay Fault Testing in Logic Circuits

  1987cited by this paper
• Book Review: Principles of CMOS VLSI Design: A Systems Perspective

  1986cited by this paper
• Model for Delay Faults Based upon Paths

  1985cited by this paper

• More than a timing resilient template: a case study on reliability-oriented improvements on blade

  2018cites this paper
• At-Speed Path Delay Test

  2015cites this paper
• Design and test of latch-based circuits to maximize performance, yield, and delay test quality

  2010influential citation
• Efficient Scheduling of Path Delay Tests for Latch-Based Circuits

  2009cites this paper
• Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor

  2007cites this paper
• A Fault-Tolerant Methodology to Design Power and Thermal Noise-Aware Pipeline Architectures

  year unknowncites this paper