Automated Compiler Optimization of Multiple Vector Loads/Stores

No abstract is available for this paper.

• Publication year

  2016

• Venue

  International journal of parallel programming

• Publication date

  2016-05-16

• Fields of study

  Computer Science

• Identifiers
  DOI 10.1007/s10766-016-0485-7
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Optimizing Overlapped Memory Accesses in User-directed Vectorization

  2015cited by this paper
• Intel’s Haswell CPU Microarchitecture

  2014cited by this paper
• Efficient Exploitation of Hyper Loop Parallelism in Vectorization

  2014cited by this paper
• Practical SIMD Vectorization Techniques for Intel® Xeon Phi Coprocessors

  2013cited by this paper
• When polyhedral transformations meet SIMD code generation

  2013cited by this paper
• A stencil compiler for short-vector SIMD architectures

  2013cited by this paper
• Can traditional programming bridge the Ninja performance gap for parallel computing applications?

  2012cited by this paper
• High-performance code generation for stencil computations on GPU architectures

  2012cited by this paper
• Efficient SIMD code generation for irregular kernels

  2012cited by this paper
• A compiler framework for extracting superword level parallelism

  2012cited by this paper
• Extending OpenMP* with Vector Constructs for Modern Multicore SIMD Architectures

  2012cited by this paper
• Software

  2012cited by this paper
• An Evaluation of Vectorizing Compilers

  2011cited by this paper
• Efficient Selection of Vector Instructions Using Dynamic Programming

  2010cited by this paper
• In-Core Optimization of High-Order Stencil Computations

  2009cited by this paper
• Reference

  2008cited by this paper
• Implicit and explicit optimizations for stencil computations

  2006cited by this paper
• Auto-vectorization of interleaved data for SIMD

  2006cited by this paper
• Intel ® 64 and IA-32 Architectures Software Developer ’ s Manual

  2006cited by this paper
• Introduction to the Cell multiprocessor

  2005cited by this paper
• Generation of permutations for SIMD processors

  2005cited by this paper
• Vectorization for SIMD architectures with alignment constraints

  2004cited by this paper
• Bottlenecks in Multimedia Processing with SIMD Style Extensions and Architectural Enhancements

  2003cited by this paper
• A SIMD vectorizing compiler for digital signal processing algorithms

  2002cited by this paper
• Ultra-fast aliasing analysis using CLA

  2001cited by this paper
• Ultra-fast aliasing analysis using CLA: a million lines of C code in a second

  2001cited by this paper
• On the importance of points-to analysis and other memory disambiguation methods for C programs

  2001cited by this paper
• A Vectorizing Compiler for Multimedia Extensions

  2000cited by this paper
• Code selection for media processors with SIMD instructions

  2000cited by this paper
• Exploiting superword level parallelism with multimedia instruction sets

  2000cited by this paper
• Partial redundancy elimination in SSA form

  1999cited by this paper
• Probabilistic memory disambiguation and its application to data speculation

  1999cited by this paper
• Memory disambiguation to facilitate instruction-level parallelism compilation

  1995cited by this paper
• Compiler technology for future microprocessors

  1995cited by this paper
• Effective partial redundancy elimination

  1994cited by this paper
• The multiflow trace scheduling compiler

  1993cited by this paper

• Exploiting Dynamic Regular Patterns in Irregular Programs for Efficient Vectorization

  2025cites this paper
• A Comprehensive Survey of Benchmarks for Improvement of Software's Non-Functional Properties

  2022cites this paper
• PROGRAMSYNTHESIS FOR SCIENTIFIC COMPUTING

  2021cites this paper
• Report of the Workshop on Program Synthesis for Scientific Computing

  2021cites this paper
• Flynn’s Reconciliation

  2021cites this paper
• ReCoTOS: A Methodology for Vectorization-based Resource-saving Computing Task Optimization

  2020cites this paper
• Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator

  2019cites this paper
• Vectorization of High-performance Scientific Calculations Using AVX-512 Intruction Set

  2019cites this paper