PipeRench: A Reconfigurable Architecture and Compiler

No abstract is available for this paper.

• Publication year

  2000

• Venue

  Computer

• Publication date

  2000-04-01

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/2.839324
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Pipeline Reconfigurable FPGAs

  2000cited by this paper
• PipeRench: a coprocessor for streaming multimedia acceleration

  1999cited by this paper
• Fast compilation for pipelined reconfigurable fabrics

  1999cited by this paper
• Detecting and Exploiting Narrow Bitwidth Computations

  1999cited by this paper
• IDEA: A Cipher For Multimedia Architectures?

  1998cited by this paper
• Recent Developments in the Design of Conventional Cryptographic Algorithms

  1997cited by this paper

• PEDC: A High-Efficacy, Parallel, and Configurable Distributed Control Architecture Design Approach of Cryptographic CGRA Utilizing the Control Subgraph Partitioning and Expansion Method

  2026cites this paper
• NUPEA: Optimizing Critical Loads on Spatial Dataflow Architectures via Non-Uniform Processing-Element Access

  2025cites this paper
• Nexus Machine: An Energy-Efficient Active Message Inspired Reconfigurable Architecture

  2025cites this paper
• Nexus Machine: An Active Message Inspired Reconfigurable Architecture for Irregular Workloads

  2025cites this paper
• Compilation Framework for Dynamically Reconfigurable Array Architectures

  2025cites this paper
• DPTM: An Adaptive Scheduler Design Utilizing Timeslot Matching and Release Methods for Concurrent and Multi-task Interleaved Pipelining-oriented CGRA

  2025cites this paper
• Ripple: Asynchronous Programming for Spatial Dataflow Architectures

  2025cites this paper
• A Coarse Grained Reconfigurable Architecture for the Realization of Turbo Encoder

  2024cites this paper
• In-memory computing: characteristics, spintronics, and neural network applications insights

  2024cites this paper
• FlowCert: Translation Validation for Asynchronous Dataflow via Dynamic Fractional Permissions

  2024cites this paper
• Enhancing CGRA Efficiency Through Aligned Compute and Communication Provisioning

  2024cites this paper
• CGRA4ML: A Hardware/Software Framework to Implement Neural Networks for Scientific Edge Computing

  2024cites this paper
• The TYR Dataflow Architecture: Improving Locality by Taming Parallelism

  2024cites this paper
• Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA

  2024cites this paper
• FLEX: Introducing FLEXible Execution on CGRA with Spatio-Temporal Vector Dataflow

  2023cites this paper
• LightTrader: A Standalone High-Frequency Trading System with Deep Learning Inference Accelerators and Proactive Scheduler

  2023cites this paper
• Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC

  2023cites this paper
• Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC

  2023cites this paper
• Pipestitch: An energy-minimal dataflow architecture with lightweight threads

  2023cites this paper
• WaveCert: Translation Validation for Asynchronous Dataflow Programs via Dynamic Fractional Permissions

  2023cites this paper
• MESA: Microarchitecture Extensions for Spatial Architecture Generation

  2023cites this paper
• Towards Efficient Control Flow Handling in Spatial Architecture via Architecting the Control Flow Plane

  2023cites this paper
• A programmable, energy-minimal dataflow compiler and architecture

  2022cites this paper
• Design and Implementation of a Coarse-grained Dynamically Reconfigurable Multimedia Accelerator

  2022cites this paper
• Twenty Years of Automated Methods for Mapping Applications on CGRA

  2022cites this paper
• Snafu: An Ultra-Low-Power, Energy-Minimal CGRA-Generation Framework and Architecture

  2021cites this paper
• Fifer: Practical Acceleration of Irregular Applications on Reconfigurable Architectures

  2021cites this paper
• Coarse-Grained Reconfigurable Computing with the Versat Architecture

  2021cites this paper
• Field-Programmable Gate Array

  2021cites this paper
• SARA: Scaling a Reconfigurable Dataflow Accelerator

  2021cites this paper
• CGRA Background and Related Work

  2021cites this paper
• Plasticity-on-Chip Design: Exploiting Self-Similarity for Data Communications

  2021cites this paper
• An Elastic Task Scheduling Scheme on Coarse-Grained Reconfigurable Architectures

  2021cites this paper
• Partial dynamic reconfiguration framework for FPGA: A survey with concepts, constraints and trends

  2021cites this paper
• DiAG: a dataflow-inspired architecture for general-purpose processors

  2021cites this paper
• Utilizing Virtualized Hardware Logic Computations to Benefit Multi-User Performance

  2021cites this paper
• Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration

  2020cites this paper
• FReaC Cache: Folded-logic Reconfigurable Computing in the Last Level Cache

  2020cites this paper
• PVHArray: An Energy-Efficient Reconfigurable Cryptographic Logic Array With Intelligent Mapping

  2020cites this paper
• Taurus: a data plane architecture for per-packet ML

  2020cites this paper
• Taurus: An Intelligent Data Plane

  2020cites this paper
• Evaluation and Proposal of a Lightweight Reconfigurable Accelerator for Heterogeneous Multicore

  2020cites this paper
• A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

  2020cites this paper
• An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

  2019influential citation
• Master of None Acceleration: A Comparison of Accelerator Architectures for Analytical Query Processing

  2019cites this paper
• Design Space Exploration of Accelerators for Warehouse Scale Computing

  2019cites this paper
• Analysis of Radhard Standard Cells using a Digital Processing Element Architecture as Test Bed

  2019cites this paper
• An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors

  2019cites this paper
• A Partially Shared Thin Reconfigurable Array For Multicore Processor

  2019cites this paper
• Compact Area and Performance Modelling for Coarse-Grained Reconfigurable Architectures

  2019cites this paper
• China Net: Military and Special Supercomputer Centers

  2019cites this paper
• A Survey of Coarse-Grained Reconfigurable Architecture and Design

  2019cites this paper
• Criteria and Approaches for Virtualization on Modern FPGAs

  2019cites this paper
• Computing In-Memory, Revisited

  2018cites this paper
• Exploiting Partial Reconfiguration on a Dynamic Coarse Grained Reconfigurable Architecture

  2018cites this paper
• Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems

  2018cites this paper
• Stitch: Fusible Heterogeneous Accelerators Enmeshed with Many-Core Architecture for Wearables

  2018cites this paper
• Modeling and Simulation Speed-Up of Plasma Actuators Implementing Reconfigurable Hardware

  2018cites this paper
• Research and Design of Pipeline Register Structure Based on Coarse-grained Reconfigurable Array

  2018cites this paper
• Real-Time Image and Video Processing Using High-Level Synthesis (HLS)

  2018cites this paper
• Architectures and Tools for Efficient Reconfigurable Computing

  2018cites this paper
• Interested in publishing with us ? Contact book

  2018cites this paper
• Interested in publishing with us ? Contact book

  2018cites this paper
• Energy efficient configuration unification and compression for CGRAs

  2018cites this paper
• Radiation-Induced Soft Errors

  2018cites this paper
• Interested in publishing with us ? Contact book

  2018cites this paper
• Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures

  2017cites this paper
• A survey on embedded reconfigurable architectures

  2017cites this paper
• Increasing the efficiency and feasibility of configurable computing units

  2017cites this paper
• Constructing Knowledge in an Interactive Game-Like Design Environment for STEM Education

  2017cites this paper
• Reconfigurable Computing

  2017cites this paper
• Design of a reconfigurable transcendental function generator

  2017cites this paper
• System level management of hybrid memory systems

  2017cites this paper
• Title Coarse Grained Reconfigurable Array Based Architecture forLow Power Real Time Seizure Detection

  2017cites this paper
• A Hybrid Partially Reconfigurable Overlay Supporting Just-In-Time Assembly of Custom Accelerators on FPGAs

  2017influential citation
• High-Level Synthesis Based VLSI Architectures for Video Coding

  2017cites this paper
• Design and optimization of DSP architectures for multi-context FPGA with dynamic reconfiguration

  2016influential citation
• Compiler-enabled Hardware Accelerators

  2016cites this paper
• Design of Coarse Grain Architecture with Active Reconfiguration for SoC

  2016cites this paper
• Conclusions and Future Trends

  2016cites this paper
• The Research of S-Box Based on Reconstruction Design Method

  2016cites this paper
• A Data Path Design Tool for Automatically Mapping Artificial Neural Networks on to FPGA-Based Systems

  2016cites this paper
• A Survey and Evaluation of FPGA High-Level Synthesis Tools

  2016cites this paper
• Review Paper on Coarse Grain Reconfigurable Architectures for Multimedia Application

  2016cites this paper
• The Stratix™ 10 Highly Pipelined FPGA Architecture

  2016cites this paper
• Evaluating programmable architectures for imaging and vision applications

  2016cites this paper
• Coarse grained reconfigurable architectures in the past 25 years: Overview and classification

  2016cites this paper
• Persistent gastro-oesophageal reflux symptoms despite proton pump inhibitor therapy.

  2016cites this paper
• Implementation of Fast Fourier Transform Accelerator on Coarse Grain Reconfigurable Architecture

  2016cites this paper
• Compiler Aspects of Hardware Accelerators

  2016cites this paper
• A Study of FPGA Resource Utilization for Pipelined Windowed Image Computations

  2016cites this paper
• Proceedings of the First International Workshop on Post Moore ' s Era Supercomputing

  2016influential citation
• On fast iterative mapping algorithms for stripe based coarse-grained reconfigurable architectures

  2015influential citation
• Re-configurable hardware programming in a protocol processor unit

  2015cites this paper
• Codem: software/hardware codesign for embedded multicore systems supporting hardware services

  2015cites this paper
• Virtualized FPGA Accelerators for Efficient Cloud Computing

  2015cites this paper
• System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems

  2015cites this paper
• Coarse Grained Reconfigurable Array Based Architecture for Low Power Real-Time Seizure Detection

  2015cites this paper
• A soft-core processor array for relational operators

  2015cites this paper
• ENERGY EFFICIENCY EXPLORATION OF COARSE-GRAIN RECONFIGURABLE ARCHITECTURE WITH EMERGING NONVOLATILE MEMORY

  2015cites this paper