Dynamic voltage and frequency scaling for shared resources in multicore processor designs

No abstract is available for this paper.

• Publication year

  2013

• Venue

  Design Automation Conference

• Publication date

  2013-05-29

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1145/2463209.2488874
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• ORION 2.0: A Power-Area Simulator for Interconnection Networks

  2012cited by this paper
• In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches

  2012cited by this paper
• An Optimal Control Approach to Power Management for Multi-Voltage and Frequency Islands Multiprocessor Platforms under Highly Variable Workloads

  2012cited by this paper
• Low-energy GALS NoC with FIFO - Monitoring dynamic voltage scaling

  2011cited by this paper
• The gem5 simulator

  2011influential reference
• A case for dynamic frequency tuning in on-chip networks

  2009cited by this paper
• A family of 45nm IA processors

  2009cited by this paper
• CACTI 6.0: A Tool to Model Large Caches

  2009cited by this paper
• Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication

  2009cited by this paper
• The PARSEC benchmark suite: Characterization and architectural implications

  2008cited by this paper
• Variation-adaptive feedback control for networks-on-chip with multiple clock domains

  2008cited by this paper
• Energy Scalability of On-Chip Interconnection Networks in Multicore Architectures

  2008cited by this paper
• Adaptive SRAM design for dynamic voltage scaling VLSI systems

  2007cited by this paper
• Adaptive Power Management for the On-Chip Communication Network

  2006cited by this paper
• Integrated link/CPU voltage scaling for reducing energy consumption of parallel sparse matrix applications

  2006cited by this paper
• Drowsy caches: simple techniques for reducing leakage power

  2002cited by this paper
• Power-efficient Interconnection Networks: Dynamic Voltage Scaling with Links

  2002cited by this paper

• CAPE: Criticality-Aware Performance and Energy Optimization Policy for NCFET-Based Caches

  2024cites this paper
• Game-of-Life Temperature-Aware DVFS Strategy for Tile-Based Chip Many-Core Processors

  2023cites this paper
• Thermal coupling analysis and improved dynamic temperature control algorithm for 3D-LSI

  2023cites this paper
• Dynamic uncore frequency scaling based on performance events of Web applications

  2023cites this paper
• Latency-Aware Frequency Scaling in Time-Triggered Network-on-Chip Architecture

  2023cites this paper
• Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design

  2022cites this paper
• Thermal Transient Analysis and Dynamic Temperature Control Algorithm for 3-D Stacked Chips

  2022cites this paper
• Energy Management for Energy Harvesting-Based Embedded Systems: A Systematic Mapping Study

  2020cites this paper
• Performance-Energy Trade-off in Modern CMPs

  2020cites this paper
• Models and Techniques for Green High-Performance Computing

  2020cites this paper
• DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning

  2020cites this paper
• Pursuing Extreme Power Efficiency With PPCC Guided NoC DVFS

  2020influential citation
• An Energy-Efficient Network-on-Chip Design using Reinforcement Learning

  2019cites this paper
• Dynamic Resource Management of Heterogeneous Mobile Platforms via Imitation Learning

  2019cites this paper
• Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques

  2019cites this paper
• Power , Performance , and Energy Management of Heterogeneous Architectures by Chetan

  2019cites this paper
• Power and Performance Optimization for Network-on-Chip based Many-Core Processors

  2019influential citation
• Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

  2018influential citation
• Dynamic Power Budgeting for Mobile Systems Running Graphics Workloads

  2018cites this paper
• Power mitigation of a heterogeneous multicore architecture on FPGA/ASIC by DFS/DVFS techniques

  2018cites this paper
• Invited: Efficient Reinforcement Learning for Automating Human Decision-Making in SoC Design

  2018cites this paper
• Task Assignment Algorithms for Multicore Platforms with Process Variations

  2018cites this paper
• Thread Voting DVFS for Manycore NoCs

  2018influential citation
• Power-Performance Modeling and Adaptive Management of Heterogeneous Mobile Platforms

  2018cites this paper
• LEAD: Learning-enabled Energy-Aware Dynamic Voltage/frequency scaling in NoCs

  2018cites this paper
• Comparisons of core and uncore frequency scaling modes in quantum chemistry application GAMESS

  2018cites this paper
• Network on Chip Router with Power Management Unit for Improved Network Fabric Power Efficiency

  2017cites this paper
• Network-on-Chip Design

  2017cites this paper
• Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip Network

  2017cites this paper
• Power-performance assessment of different DVFS control policies in NoCs

  2017cites this paper
• Marginal Performance: Formalizing and Quantifying Power Over/Under Provisioning in NoC DVFS

  2017influential citation
• DyPO

  2017cites this paper
• An efficient energy-driven scheduling of DVFS-multicore systems with a hierarchy of shared memories

  2017influential citation
• Fluid wireless protocols: energy-efficient design and implementation

  2017cites this paper
• 15 Network-on-Chip Design

  2017cites this paper
• A case for low frequency single cycle multi hop NoCs for energy efficiency and high performance

  2017cites this paper
• Power mitigation of a heterogeneous multicore architecture by frequency scaling in an OFDM receiver test case

  2017cites this paper
• On-Chip Networks: Second Edition

  2017cites this paper
• Ant Colony Optimization Algorithm to Dynamic Energy Management in Cloud Data Center

  2017cites this paper
• DyPO : Dynamic Pareto-Optimal Configuration Selection for Heterogeneous

  2017cites this paper
• Noc Router With Dedicated Power Management Unit

  2017cites this paper
• Head-of-Line Blocking Reduction in Power-Efficient Networks-on-Chip

  2017cites this paper
• Accurately modeling GPGPU frequency scaling with the CRISP performance model

  2017cites this paper
• Adroit Use of Dark Silicon for Power, Performance and Reliability Optimisation of NoCs

  2017cites this paper
• Automated Hardware Prototyping for 3D Network on Chips

  2017cites this paper
• Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching

  2016cites this paper
• Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory

  2016influential citation
• Power Mitigation by Performance Equalization in a Heterogeneous Reconfigurable Multicore Architecture

  2016cites this paper
• DVFS for NoCs in CMPs: A thread voting approach

  2016cites this paper
• Increasing the Efficiency of Latency-Driven DVFS with a Smart NoC Congestion Management Strategy

  2016cites this paper
• Power Management Controller for Online Power Saving in Network-on-Chips

  2016cites this paper
• Memory-access aware DVFS for network-on-chip in CMPs

  2016cites this paper
• Malleable NoC: Dark silicon inspired adaptable Network-on-Chip

  2015cites this paper
• Modeling DVFS and Power-Gating Actuators for Cycle-Accurate NoC-Based Simulators

  2015cites this paper
• Rate-based vs delay-based control for DVFS in NoC

  2015cites this paper
• 56 Gb/s PAM-4 optical receiver frontend in an advanced FinFET process

  2015cites this paper
• The CRISP performance model for dynamic voltage and frequency scaling in a GPGPU

  2015cites this paper
• Adaptive Scheduling Algorithm for Energy Harvesting Embedded System

  2015cites this paper
• SuperNet: Multimode interconnect architecture for manycore chips

  2015cites this paper
• Energy efficient voltage scheduling for multi-core processors with software controlled dynamic voltage scaling

  2014cites this paper
• Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems

  2014cites this paper
• Up by their bootstraps: Online learning in Artificial Neural Networks for CMP uncore power management

  2014influential citation
• Dark silicon as a challenge for hardware/software co-design

  2014cites this paper
• darkNoC: Designing energy-efficient network-on-chip with multi-Vt cells for dark silicon

  2014cites this paper