A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy

No abstract is available for this paper.

• Publication year

  2017

• Venue

  IEEE Transactions on Very Large Scale Integration (VLSI) Systems

• Publication date

  Unknown publication date

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/TVLSI.2016.2569532
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

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