Challenge: variability characterization and modeling for 65- to 90-nm processes

No abstract is available for this paper.

• Publication year

  2005

• Venue

  Proceedings of the IEEE Custom Integrated Circuits Conference

• Publication date

  2005-09-18

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/CICC.2005.1568738
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Design guide and process quality improvement for treatment of device variations in an LSI chip

  2004cited by this paper
• The impact of device parameter variations on the frequency and performance of VLSI chips

  2004cited by this paper
• Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

  2003cited by this paper
• On-chip wiring design challenges for gigahertz operation

  2001cited by this paper
• Harmony: static noise analysis of deep submicron digital integrated circuits

  1999cited by this paper
• Full-chip verification of UDSM designs

  1998cited by this paper
• Analysis and decomposition of spatial variation in integrated circuit processes and devices

  1997cited by this paper
• Practical engineering statistics: D. Schiff and R. B. D'Agostino, Wiley, New York, NY, 1996, 288 pages, $59.95.

  1996cited by this paper
• Matching properties of MOS transistors

  1988cited by this paper

• Model-Based Variation-Aware Optimization for Offset Calibration and Pre-Sensing in DRAM Sense Amplifiers

  2025cites this paper
• Variation-Aware Clock Path Timing Model in Near-Threshold Voltage

  2023cites this paper
• Fast and Efficient Offset Compensation by Noise-Aware Pre-Charge and Operation of DRAM Bit Line Sense Amplifier

  2023cites this paper
• Quick and Efficient Offset Compensation by Noise-Aware Operation of DRAM Bit Line Sense Amplifier

  2022cites this paper
• Joint Compensation of Jitter Noise and Time-Shift Errors in Multichannel Sampling System

  2019cites this paper
• Variability in Nanometer Technologies and Impact on SRAM

  2019cites this paper
• Recent Advance in Computational Prototyping for Analysis of High-performance Analog/RF ICs

  2019cites this paper
• Методы верификации на кристалле задержек распространения стандартных цифровых элементов

  2018cites this paper
• Recent Advance in Computational Prototyping for Analysis of High-performance Analog/RF ICs

  2018cites this paper
• Gate Delay Under Process Variations

  2018cites this paper
• Experimental study of the Adaptive Body Bias on-Chip (ABBoC) for bias temperature instability (BTI) and Process Variations (PV) compensation

  2018cites this paper
• Recent Advance in Computational Prototyping for Analysis of High-performance Analog/RF ICs

  2018cites this paper
• FOR YIELD FOR SUB-22 nm FinFET-BASED FPGA

  2016cites this paper
• Statistical Rare-Event Analysis and Parameter Guidance by Elite Learning Sample Selection

  2016cites this paper
• Towards automatic gain control low-power amplifier in 130 nm CMOS technology

  2016cites this paper
• Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent Manufacturability Evaluation

  2016cites this paper
• Characterization of an O2 sensor using microelectrodes

  2016cites this paper
• DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout

  2016cites this paper
• Lifetime Reliability Enhancement of Microprocessors

  2015cites this paper
• Current Sensing Completion Detection in Single-Rail Asynchronous Systems

  2015cites this paper
• Subblock-level matching layout for analog block-pair and its manufacturability evaluation

  2015cites this paper
• City Research Online

  2015cites this paper
• GPU-accelerated parallel Monte Carlo analysis of analog circuits by hierarchical graph-based solver

  2015cites this paper
• Statistical rare event analysis using smart sampling and parameter guidance

  2015cites this paper
• Signal Reconstruction Algorithms for Time-Interleaved ADCs

  2015cites this paper
• Rare event diagnosis by iterative failure region locating and elite learning sample selection

  2015cites this paper
• Building Blocks for Low-Voltage Analog-to-Digital Interfaces

  2014cites this paper
• MINIMISING AGING EFFECTS ON THRESHOLD USING ADAPTIVE BODY BIAS

  2014cites this paper
• A design-oriented timing jitter/skew model in voltage-to-time converter (VTC) circuits

  2014cites this paper
• Design Optimization of Multigate Bulk MOSFETs

  2013cites this paper
• Statistical SRAM Read Access Yield Improvement Using Negative Capacitance Circuits

  2013cites this paper
• Performance bound analysis of analog circuits in frequency- and time-domain considering process variations

  2013cites this paper
• Negative capacitance circuits for process variations compensation and timing yield improvement

  2013cites this paper
• A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)

  2013cites this paper
• Delay Characterization in FPGA-based Reconfigurable Systems

  2013cites this paper
• Completion detection in dual-rail asynchronous systems by current-sensing

  2013cites this paper
• Extracting device-parameter variations using a single sensitivity-configurable ring oscillator

  2013cites this paper
• Parallel and Statistical Analysis and Modeling of Nanometer VLSI Systems

  2013cites this paper
• A gate-delay model focusing on current fluctuation over wide range of process-voltage-temperature variations

  2013cites this paper
• Variability in Nanometer Technologies and Impact on SRAM

  2013cites this paper
• Time-domain performance bound analysis of analog circuits considering process variations

  2012cites this paper
• A monitoring infrastructure for FPGA self-awareness and dynamic adaptation

  2012cites this paper
• NBTI and Process Variations Compensation Circuits Using Adaptive Body Bias

  2012cites this paper
• Layout-Aware Variability Characterization of CMOS Current Sources

  2012cites this paper
• Parallel statistical analysis of analog circuits by GPU-accelerated graph-based approach

  2012cites this paper
• Performance Bound Analysis of Variational Linearized Analog Circuits

  2012cites this paper
• Variational analysis of analog integrated circuits based on symbolic analysis

  2012cites this paper
• Low-voltage current sensor design in 90 nm CMOS technology

  2012cites this paper
• Comparison of modeling techniques in circuit variability analysis

  2012cites this paper
• Modeling transistor variation using α-power formula and its application to sensitivity analysis on harmonic distortion in differential amplifier

  2012cites this paper
• On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS

  2012cites this paper
• Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

  2012cites this paper
• Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

  2012cites this paper
• A High Performance Switched Capacitor-Based DC-DC Buck Converter Suitable for Embedded Power Management Applications

  2012cites this paper
• On-Chip Process Variations Compensation Using an Analog Adaptive Body Bias (A-ABB)

  2012cites this paper
• Current sensing completion detection in dual-rail asynchronous systems

  2012cites this paper
• Variation-Tolerant Adaptive Voltage Systems

  2012cites this paper
• Stochastic Analog Mismatch Analysis

  2012cites this paper
• Layout-aware variation evaluation of analog circuits and its validity on op-amp designs

  2011cites this paper
• Statistical Design Framework of Submicron Flip-Flop Circuits Considering Process Variations

  2011cites this paper
• Performance bound analysis of analog circuits considering process variations

  2011cites this paper
• The effects of process variations on performance and robustness of bulk CMOS and SOI implementations of C-elements

  2011cites this paper
• Modeling transistor variation using α-power formula and its application to sensitivity analysis on harmonic distortion in differential amplifier

  2011cites this paper
• Low-Cost Highly-Efficient Fault Tolerant Processor Design for Mitigating the Reliability Issues in Nanometric Technologies

  2011cites this paper
• Extracting Device-Parameter Variations with RO-Based Sensors

  2011cites this paper
• Design of High-Speed Analog-to-Digital Converters using Low-Accuracy Components

  2011cites this paper
• Monte Carlo Analysis of Propagation Delay Deviation due to Process Induced Line Parasitic Variations in Global VLSI Interconnects

  2011cites this paper
• Novel Timing Yield Improvement Circuits for High-Performance Low-Power Wide Fan-In Dynamic OR Gates

  2011cites this paper
• Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis

  2011cites this paper
• Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells

  2011influential citation
• Nanoscale Microelectronic Circuit Development

  2011cites this paper
• Monte Carlo analysis of propagation delay due to process induced line parasitic variations in VLSI interconnects

  2011cites this paper
• Robustness in analog systems: Design techniques, methodologies and tools

  2011cites this paper
• Evolution in Networks and Computer Communications

  2011cites this paper
• Electrical Design for Manufacturability Solutions: Fast Systematic Variation Analysis and Design Enhancement Techniques

  2011cites this paper
• Robust Design of Variation-Sensitive Digital Circuits

  2011cites this paper
• An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS

  2011cites this paper
• Propagation delay deviations due to process induced line parasitic variations in global VLSI interconnects

  2011cites this paper
• Mismatch Simulation of Motion Detection Pointing Device

  2011cites this paper
• Uncertainty Propagation in Transistor-level Statistical Circuit Analysis

  2011cites this paper
• Managing Temperature Effects in Nanoscale Adaptive Systems

  2011cites this paper
• Device-parameter estimation with on-chip variation sensors considering random variability

  2011cites this paper
• A Novel Low Area Overhead Direct Adaptive Body Bias (D-ABB) Circuit for Die-to-Die and Within-Die Variations Compensation

  2011cites this paper
• Variation Study of the Planar Ground-Plane Bulk MOSFET, SOI FinFET, and Trigate Bulk MOSFET Designs

  2011cites this paper
• Prediction of Circuit-Performance Variations from Technology Variations for Reliable 100 nm SOC Circuit Design

  2011cites this paper
• Process Compensation Loops for High Speed Ring Oscillators in Sub-Micron CMOS

  2011cites this paper
• A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

  2010influential citation
• D-A converter based variation analysis for analog layout design

  2010cites this paper
• Design and Run-time Reliability at the Electronic System Level

  2010cites this paper
• Statistical Yield Analysis and Design for Nanometer VLSI

  2010cites this paper
• Variability Analysis of Inverter Delay Time

  2010cites this paper
• Accuracy Enhancement of Grid-Based SSTA by Coefficient Interpolation

  2010cites this paper
• A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

  2010cites this paper
• Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits

  2010cites this paper
• Fine-grained characterization of process variation in FPGAs

  2010cites this paper
• A fast analog mismatch analysis by an incremental and stochastic trajectory piecewise linear macromodel

  2010cites this paper
• Statistical Timing Analysis Considering Clock Jitter and Skew due to Power Supply Noise and Process Variation

  2010cites this paper
• Nanoscale Bulk MOSFET Design and Process Technology for Reduced Variability

  2010influential citation
• Statistical timing yield improvement of dynamic circuits using negative capacitance technique

  2010cites this paper
• Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch

  2010cites this paper