A Min-Cut Placement Algorithm for General Cell Assemblies Based on a Graph Representation

No abstract is available for this paper.

• Publication year

  1979

• Venue

  Design Automation Conference

• Publication date

  1979-06-25

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1145/62882.62901
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• A class of min-cut placement algorithms

  1988cited by this paper
• Methods for Hierarchical Automatic Layout of Custom LSI Circuit Masks

  1978cited by this paper
• The siemens-avesta-system for computer-aided design of MOS-standard cell circuits

  1977cited by this paper
• A proper model for the partitioning of electrical circuits

  1972cited by this paper
• Depth-First Search and Linear Graph Algorithms

  1972cited by this paper
• An integrated circuit layout design program based on a graph-theoretical approach

  1970cited by this paper
• An efficient heuristic procedure for partitioning graphs

  1970cited by this paper
• The Dissection of Rectangles Into Squares

  1940cited by this paper

• TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design

  2022cites this paper
• AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs

  2021cites this paper
• Robustness-oriented k Edge Server Placement

  2020cites this paper
• Evolution of CAD tools towards third generation custom VLSI design

  2019cites this paper
• Integration of AI and OR Techniques in Constraint Programming: 12th International Conference, CPAIOR 2015, Barcelona, Spain, May 18-22, 2015, Proceedings

  2015cites this paper
• Rectangle Placement for VLSI Testing

  2015cites this paper
• Improving biological significance of gene expression biclusters with key missing genes

  2015cites this paper
• Application-Specific Heterogeneous Network-on-Chip Design

  2014cites this paper
• A finite domain constraint approach for placement and routing of coarse-grained reconfigurable architectures

  2010cites this paper
• The continuous hopfield networks (CHN) for the placement of the electronic circuits problem

  2009cites this paper
• Efficient Quadratic Placement of VLSI Circuits

  2008cites this paper
• Slicing Floorplan Orientation

  2008cites this paper
• A fast and efficient two-dimensional frame composer for OFDMA WiMAX base-stations using floorplan slicing

  2008cites this paper
• Digital Phase Locked Loop Interface Design

  2007cites this paper
• Corner block list representation and its application with boundary constraints

  2004cites this paper
• A linear programming-based algorithm for floorplanning in VLSI design

  2003cites this paper
• The Best of ICCAD

  2003cites this paper
• The optimisation of block layout and aisle structure by a genetic algorithm

  2002cites this paper
• Integrated design of the block layout and aisle structure by simulated annealing

  2002cites this paper
• Fast floorplanning for effective prediction and construction

  2001cites this paper
• Modeling layout tools to derive forward estimates of area and delay at the RTL level

  2000cites this paper
• Algorithmic and theoretical problems related to the physical design of three dimensional field programmable gate arrays

  2000cites this paper
• A design flow for performance planning: new paradigms for iteration free synthesis

  2000cites this paper
• A FLOORPLANNING-SYNTHESIS METHODOLOGY FOR MULTIPLE CHIP MODULE DESIGN

  2000cites this paper
• Fast hierarchical floorplanning with congestion and timing control

  2000cites this paper
• A snap-on placement tool

  2000cites this paper
• Attractor-repeller approach for global placement

  1999cites this paper
• A technology-independent methodology of placement generation for analog circuit

  1999cites this paper
• A robust solution to the timing convergence problem in high-performance design

  1999cites this paper
• An automated method for data path construction

  1998cites this paper
• CASH: a novel quadratic placement algorithm for very large standard cell layout design based on clustering

  1998cites this paper
• VEAP: Global optimization based efficient algorithm for VLSI placement

  1997cites this paper
• VLSI circuit placement with rectilinear modules using three-layer force-directed self-organizing maps

  1997cites this paper
• VEAP: Global optimization based efficient algorithm for VLSI placement

  1997cites this paper
• Partitioning-based standard-cell global placement with an exact objective

  1997cites this paper
• VEAP : Global Optimization based Efficient Algorithm for

  1997cites this paper
• Timing-driven placement for regular architectures

  1997cites this paper
• EMC-driven placement for MCM

  1997cites this paper
• Hierarchical placement for power hybrid circuits under reliability and wireability constraints

  1996cites this paper
• Parallel algorithms for standard cell placement using simulated annealing

  1996cites this paper
• Scheduling as a multi-dimensional placement problem

  1996cites this paper
• A complete design path for the layout of flexible macros

  1996cites this paper
• A NEW LAYOUT DESIGN SYSTEM FOR MULTICHIP MODULES

  1995cites this paper
• Geometric interconnection and placement algorithms

  1995influential citation
• The crossing distribution problem [IC layout]

  1995cites this paper
• Risa: Accurate And Efficient Placement Routability Modeling

  1994cites this paper
• Iterative placement improvement by network flow methods

  1994cites this paper
• Multi-level Logic Optimization By Implication Analysis

  1994cites this paper
• Technology Mapping for VLSI Circuits Exploiting Boolean Properties and Operations

  1994cites this paper
• Building Rectangular Floorplans-A Graph Theoretical Approach

  1994cites this paper
• Quadratic 0/1 optimization and a decomposition approach for the placement of electronic circuits

  1994cites this paper
• Compression-relaxation: A New Approach To Performance Driven Placement For Regular Architectures

  1994cites this paper
• Rapid Prototyping of Printed Circuit Boards

  1994cites this paper
• A new approach to floorplan area optimization: to slice or not to slice?

  1994cites this paper
• A class of zero wasted area floorplan for VLSI design

  1993cites this paper
• Architectures for Parallel Slicing Enumeration in VLSI Layout

  1993cites this paper
• A Parallel VLSI Circuit Layout Methodology

  1993cites this paper
• A new schematic-driven floorplanning algorithm for analog cell layout

  1993cites this paper
• An automatic placement tool for rapid prototyping of printed circuit boards

  1993cites this paper
• Optimization-based placement algorithms for BiCMOS leaf cell generation

  1993cites this paper
• A fast parallel algorithm for slicing floorplans

  1993cites this paper
• Optimum area minimization for nonslicing floorplan [VLSI layout]

  1993cites this paper
• Algorithmic Aspects of VLSI Layout

  1993cites this paper
• Graph-based techniques to speed up floorplan area optimization

  1993cites this paper
• A graph theoretic technique to speed up floorplan area optimization

  1992cites this paper
• Optimal floorplan area optimization

  1992cites this paper
• Early wirability checking and 2D congestion-driven circuit placement

  1992cites this paper
• Fasolt: a program for feedback-driven data-path optimization

  1992cites this paper
• Parallel algorithms for slicing based final placement

  1992cites this paper
• Circuit placement on arbitrarily shaped regions using the self-organization principle

  1992cites this paper
• Analogy between VLSI floorplanning problems and realisation of a resistive network

  1992cites this paper
• Macro-cell and module placement by genetic adaptive search with bitmap-represented chromosome

  1991cites this paper
• The Crossing Distribution Problem

  1991cites this paper
• An analytic net weighting approach for performance optimization in circuit placement

  1991cites this paper
• Analytical placement: a linear or a quadratic objective function?

  1991cites this paper
• Area optimization for general floorplans: an analogy to resistive networks

  1991cites this paper
• A high density placement algorithm based on simulated surface tension

  1991cites this paper
• Global placement of macro cells using self-organization principle

  1991cites this paper
• Floorplanning strategy for mixed analog-digital VLSI integrated circuits

  1991cites this paper
• Branch-and-bound placement for building block layout

  1991cites this paper
• An efficient heuristic for standard-cell placement

  1991cites this paper
• Towards optimizing global mincut partitioning

  1991cites this paper
• VLSI cell placement techniques

  1991cites this paper
• Datapath optimization using feedback

  1991cites this paper
• A cell-replicating approach to minicut-based circuit partitioning

  1991cites this paper
• Goal orientated slicing enumeration through shape function clipping

  1991cites this paper
• Area optimization for higher order hierarchical floorplans

  1991cites this paper
• SHARP-looking geometric partitioning

  1991cites this paper
• GORDIAN: VLSI placement by quadratic programming and slicing optimization

  1991cites this paper
• Modelling co-operative knowledge systems in design

  1991cites this paper
• Compacting dead space in partitioning methods for random cells placements

  1991cites this paper
• The crossing distribution problem

  1991cites this paper
• Recent advances in VLSI layout

  1990cites this paper
• An optimal algorithm for floorplan area optimization

  1990cites this paper
• Circuit Partitioning with Genetic Algorithms Using a Coding Scheme to Preserve the Structure of a Circuit

  1990cites this paper
• Hierarchical Physical Design of Complex VLSI Circuits

  1990cites this paper
• Congestion-driven placement using a new multi-partitioning heuristic

  1990cites this paper
• VLSI-placement based on routing and timing information

  1990cites this paper
• An ADVANCELL 1.0 mainframe chipset-2.2 million transistors on 11 ICs

  1990cites this paper
• Recent Advances in VLSl Layout

  1990cites this paper