Minimum area cost for a 30 to 70 Gbits/s AES processor

No abstract is available for this paper.

• Publication year

  2004

• Venue

  IEEE Computer Society Annual Symposium on VLSI

• Publication date

  2004-10-04

• Fields of study

  Computer Science, Engineering

• Identifiers
  DOI 10.1109/ISVLSI.2004.1339512
• External record

  Open on Semantic Scholar

• Source metadata

  Semantic Scholar

• No claims are published for this paper.

• No concepts are published for this paper.

• Speed-area trade-off for 10 to 100 Gbits/s throughput AES processor

  2003cited by this paper
• Design and performance testing of a 2.29-GB/s Rijndael processor

  2003cited by this paper
• A 2.29 Gbits/sec, 56 mW non-pipelined Rijndael AES encryption IC in a 1.8 V, 0.18 /spl mu/m CMOS technology

  2002cited by this paper
• An ASIC Implementation of the AES SBoxes

  2002cited by this paper
• An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists

  2001cited by this paper
• A Compact Rijndael Hardware Architecture with S-Box Optimization

  2001cited by this paper
• High Performance Single-Chip FPGA Rijndael Algorithm Implementations

  2001cited by this paper
• SP 800-38A 2001 edition. Recommendation for Block Cipher Modes of Operation: Methods and Techniques

  2001cited by this paper
• Efficient Implementation of the Rijndael S-box

  2000cited by this paper
• Hardware Evaluation of the AES Finalists

  2000cited by this paper

• Non-Linear Cyclic Variable Clock Feistel Bridge-Inspired Countermeasure for Securing RISC-V Crypto-Core Against Power Attacks

  2025cites this paper
• MTDCAP: Moving Target Defense-Based CAN Authentication Protocol

  2024cites this paper
• Securing AES Designs Against Power Analysis Attacks: A Survey

  2023cites this paper
• Exploring the high-throughput and low-delay hardware design of SM4 on FPGA

  2022cites this paper
• A design solution to reduce electrical/electronic complexity with secured CAN architecture for an automotive power system

  2020cites this paper
• Scalable Data Storage Design for Nonstationary IoT Environment With Adaptive Security and Reliability

  2020cites this paper
• CAN ID Shuffling Technique (CIST): Moving Target Defense Strategy for Protecting In-Vehicle CAN

  2019influential citation
• Speedup for Cryptography on CUDA Heterogeneous Architecture

  2019cites this paper
• AR-RRNS: Configurable reliable distributed data storage systems for Internet of Things to ensure security

  2017influential citation
• Application of the Codes of a Polynomial Residue Number System , Aimed at Reducing the Effects of Failures in the AES Cipher

  2016cites this paper
• FPGA IMPLEMENTATION OF AREA OPTIMIZED AES ALGORITHM FOR SECURE COMMUNICATION APPLICATIONS

  2016cites this paper
• The development and researching of lightweight pseudorandom number generators

  2016cites this paper
• A Practical Security Architecture for In-Vehicle CAN-FD

  2016cites this paper
• AES in partially reconfigurable CGRAs

  2016cites this paper
• Легковесная криптография. Часть 1

  2015cites this paper
• A Practical Wireless Attack on the Connected Car and Security Protocol for In-Vehicle CAN

  2015cites this paper
• COMPARATIVE ANALYSIS OF FPGA DESIGN OF AES CORE ARCHITECTURE FOR EXTERNAL MEMORY DEVICE

  2014cites this paper
• Design of a Specific Instructions Set Processor for AES Algorithm

  2014cites this paper
• Embedded 8-bit AES in wireless Bluetooth application

  2013cites this paper
• ASIC Implementation of Switchable Key AES Cryptoprocessor

  2013cites this paper
• Design of High Security and Performance System for Storage Devices Using AES

  2013cites this paper
• An Ultrahigh Speed AES Processor Method Based on FPGA

  2013cites this paper
• Analyzing and comparing the AES architectures for their power consumption

  2012cites this paper
• LOW POWER ASIC IMPLEMENTATION OF A 256 BIT KEY AES CRYPTO-PROCESSOR AT 45NM TECHNOLOGY

  2012cites this paper
• A FPGA design of AES core architecture for portable hard disk

  2011cites this paper
• A Compact 8-Bit AES Crypto-processor

  2010cites this paper
• Enhancing the Performance of Symmetric-Key Cryptography via Instruction Set Extensions

  2010influential citation
• Design feasibility study for a 500 Gbits/s advanced encryption standard cipher/decipher engine

  2010cites this paper
• Instruction set extensions for the advanced encryption standard on a multithreaded software defined radio platform

  2010cites this paper
• VLSI circuits for cryptographic authentication

  2010cites this paper
• CUDA-based AES parallelization with fine-tuned GPU memory utilization

  2010cites this paper
• SLICED: Slide-based concurrent error detection technique for symmetric block ciphers

  2010cites this paper
• Experiments for Accelerating IEEE 802 . 11 i on Cyclone II FPGA

  2010cites this paper
• Design and analysis of a high performance AES processor

  2010influential citation
• Single- and Multi-core Configurable AES Architectures for Flexible Security

  2010cites this paper
• New Experimental Results for AES-CCMP Acceleration on Cyclone-II FPGA

  2010cites this paper
• Designing AES cryptographic unit for automatic implementation in low-cost FPGA devices

  2010cites this paper
• Novel countermeasures and techniques for differential power analysis

  2009cites this paper
• Design of a High Speed and Low Latency

  2008cites this paper
• Chai-Tea, Cryptographic Hardware Implementations of xTEA

  2008cites this paper
• Organization of AES Cryptographic Unit for Low Cost FPGA Implementation

  2008cites this paper
• Design of a high speed and low latency crypto-processor ASIC

  2008cites this paper
• Accelerated AES implementations via generalized instruction set extensions

  2008influential citation
• The SHAvite-3 Hash Function

  2008cites this paper
• 8-bit AES FPGA Implementation using Block RAM

  2007cites this paper
• Accelerating memory decryption and authentication with frequent value prediction

  2007influential citation
• Trust: Transaction History Based Peer-to-Peer Trust Model

  2007cites this paper
• I2SEMS: Interconnects-Independent Security Enhanced Shared Memory Multiprocessor Systems

  2007cites this paper
• Compact FPGA implementation of 32-bits AES algorithm using Block RAM

  2007cites this paper
• FPGA IMPLEMENTATION OF THE AES ENCRYPTION AND DECRYPTION ALGORITHMS

  2007cites this paper
• A Comprehensive Framework for Enhancing Security in InfiniBand Architecture

  2007cites this paper
• CUDA Compatible GPU as an Efficient Hardware Accelerator for AES Cryptography

  2007cites this paper
• 8-bit AES Implementation in FPGA by Multiplexing 32-bit AES Operation

  2007cites this paper
• The AES Design Space Exploration with a Soft IP Generator

  2007cites this paper
• AES Encryption Implementation and Analysis on Commodity Graphics Processing Units

  2007cites this paper
• I 2 SEMS: Interconnects-Independent Security Enhanced Shared Memory

  2007cites this paper
• Authentication Control Point and Its Implications For Secure Processor Design

  2006cites this paper
• Compiler and Architectural Approaches to Software Protection and Security

  2006cites this paper
• Architectural Support for Protecting Memory Integrity and Confidentiality

  2006influential citation
• Parity Prediction of S-Box for AES

  2006influential citation
• FastPass: Providing First-Packet Delivery

  2006cites this paper
• Process Isolation for Reconfigurable Hardware

  2006cites this paper
• An improvement to a biometric.based multimedia content protection scheme

  2006cites this paper
• Design Feasibility Study For A 500 Gbits/s AES Cypher Decypher Engine

  2006cites this paper
• A METHODOLOGY FOR HARDWARE TASKS SCHEDULING OPTIMIZED IN TIME FOR PARTIAL AND DYNAMIC RECONFIGURATION OF FPGAS

  2005cites this paper
• A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512

  2005influential citation
• State of the Art in Hardware Architectures

  2005cites this paper
• Incorporating error detection and online reconfiguration into a regular architecture for the advanced encryption standard

  2005cites this paper
• Security enhancement in InfiniBand architecture

  2005cites this paper
• Compact hardware implementation of advanced encryption standard with concurrent error detection

  2005influential citation
• System-on-chip implementation of the whole advanced encryption standard processor using reduced XOR-based sum-of-product operations

  2005cites this paper
• A multi-purpose cryptographic primitive with integrated family keying support providing encryption , keyed message authentication and collision resistant hashing , targeted to semi-conductor applications

  2005influential citation
• Block diagram of Rijndael ’ s AES : ( a ) Key Schedule , ( b ) Encryption

  2005cites this paper
• High efficiency counter mode security architecture via prediction and precomputation

  2005cites this paper
• Improving memory encryption performance in secure processors

  2005cites this paper
• SENSS: security enhancement to symmetric shared memory multiprocessors

  2005cites this paper
• A 3.84 gbits/s AES crypto coprocessor with modes of operation in a 0.18-μm CMOS technology

  2005cites this paper
• Streaming encryption for a secure wavelength and time domain hopped optical network

  2004cites this paper
• Exploring Area/Delay Tradeoffs in an AES FPGA Implementation

  2004influential citation
• Design-space exploration of the most widely used cryptography algorithms

  2004cites this paper
• A Secure Multithreaded Coprocessor Interface ÿ ÿ

  year unknowncites this paper
• A 3.84 Gbits/s AES Crypto Coprocessor with Modes of Operation in a 0.18-(cid:255) m CMOS Technology

  year unknowncites this paper